r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 317

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

(b) Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space
write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to
be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit
in DRACCR. Figure 6.90 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
(8)
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM
Space Access:
Group.
UCAS, LCAS
Address bus
Figure 6.90 Example of Idle Cycle Operation after DRAM Write Access
HWR, LWR
Data bus
RAS
RD
φ
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
T
p
DRAM space read
T
r
T
c1
T
c2
Idle cycle
T
i
External space read
T
1
Rev. 1.00 Sep. 19, 2008 Page 289 of 1270
T
2
T
Section 6 Bus Controller (BSC)
3
DRAM space read
T
c1
T
c2
REJ09B0466-0100