mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 143

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Frame Header Section Access
The frame header is located in the FRM. To ensure data consistency, the application must follow the write
access scheme described below.
For receive message buffers, receive shadow buffers, and receive FIFOs, the application must not write to
the frame header field.
For transmit message buffers, the application must follow the write access restrictions given in
This table shows the condition under which the application can write to the frame header entries. In
general, the application can modify all frame header entries when the protocol is in the
or when the message buffer is disabled. For message buffers assigned to the dynamic segment, the
application can modify all frame header entries except the frame ID when the message buffer is locked.
The frame header entries NUF, SYF, SUF, and CYCCNT are not used for frame transmission. These values
are generated internally before frame transmission depending on the current transmission state and
configuration.
For transmit message buffers assigned to the static segment, the PLDLEN value must be equal to the value
of the payload_length_static field in the
fulfilled, the static payload length error flag SPL_EF in the
when the message buffer is under transmission. The PE generates a syntactically and semantically correct
frame with payload_length_static payload words and the payload length field in the frame header set to
payload_length_static.
Freescale Semiconductor
NUF, SYF
CYCCNT
0x0
0x2
0x4
PLDLEN
HDCRD
R*, PPI
Field
SUF
FID
R*
15
POC:config
= not used for TX message buffers, not updated for RX message buffers
Segment
MB_DIS
PPI
Static
14
or
Single Buffered
NUF
13
POC:config
Dynamic
Segment
SYF
MB_LCK
MB_DIS
12
Table 3-80. Frame Header Write Access Constraints
or
or
SUF
11
CYCCNT
Figure 3-102. Frame Header Structure
Commit Side
10
MFR4300 Data Sheet, Rev. 3
Protocol Configuration Register 19
9
Static Segment
POC:config
POC:config
MB_DIS
8
or
Transmit Side
TX
7
or MB_DIS
CHI Error Flag Register (CHIERFR)
Double Buffered
6
HDCRC
FID
5
Commit Side
POC:config
MB_LCK
MB_DIS
(PCR19). If this is not
4
or
or
PLDLEN
Dynamic Segment
FlexRay Module (FLEXRAYV2)
3
POC:config
2
Transmit Side
POC:config
MB_DIS
Table
1
or
is set
3-80.
state
0
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