mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 83

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.3.2.14
Freescale Semiconductor
0x001E
Reset
TBVB_IE
TBVA_IE
LTXB_IE
LTXA_IE
MOC_IE
MXS_IE
CCL_IE
MTX_IE
CYS_IE
TI2_IE
TI1_IE
W
Field
R
10
9
8
7
6
5
4
3
2
1
0
15
0
Missing Offset Correction Interrupt Enable — This bit controls MOC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Clock Correction Limit Reached Interrupt Enable — This bit controls CCL_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Max Sync Frames Detected Interrupt Enable — This bit controls MXS_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Media Access Test Symbol Received Interrupt Enable — This bit controls MTX_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
pLatestTx
0 interrupt request generation disabled
1 interrupt request generation enabled
pLatestTx
0 interrupt request generation disabled
1 interrupt request generation enabled
Transmission across boundary on channel B Interrupt Enable — This bit controls TBVB_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Transmission across boundary on channel A Interrupt Enable — This bit controls TBVA_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Timer 2 Expired Interrupt Enable — This bit controls TI1_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Timer 1 Expired Interrupt Enable — This bit controls TI1_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Cycle Start Interrupt Enable — This bit controls CYC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Protocol Interrupt Enable Register 1 (PIER1)
14
0
13
0
Violation on Channel B Interrupt Enable — This bit controls LTXB_IF interrupt request generation.
Violation on Channel A Interrupt Enable — This bit controls LTXA_IF interrupt request generation.
Figure 3-13. Protocol Interrupt Enable Register 1 (PIER1)
12
0
Table 3-19. PIER0 Field Descriptions (Continued)
11
0
10
0
MFR4300 Data Sheet, Rev. 3
0
9
0
8
Description
0
0
7
6
0
0
0
5
0
4
FlexRay Module (FLEXRAYV2)
0
0
3
0
0
2
Write: Any Time
1
0
0
0
0
0
83