mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 98

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

FlexRay Module (FLEXRAYV2)
3.3.2.30
This register provides the number of synchronization frames that are used for clock synchronization in the
last even and in the last odd numbered communication cycle. This register is updated after the NIT start
and before 10 MT after offset correction start.
3.3.2.31
This register defines the FRM related offset for Sync Frame Tables. For more details, see
“Sync Frame ID and Sync Frame Deviation
98
0x0040
0x0042
Reset
Reset
SFODB
SFODA
SFEVB
SFEVB
W
15–12
W
Field
R
11–8
R
7–4
3–0
15
15
0
0
Sync Frames Channel B, even cycle — protocol related variable: size of
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
Sync Frames Channel A, even cycle — protocol related variable: size of
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
Sync Frames Channel B, odd cycle — protocol related variable: size of
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
Sync Frames Channel A, odd cycle — protocol related variable: size of
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
Sync Frame Counter Register (SFCNTR)
Sync Frame Table Offset Register (SFTOR)
14
14
0
0
If the application has locked the even synchronization table at the end of the
static segment of an even communication cycle, the FlexRay module will
not update the fields SFEVB and SFEVA.
If the application has locked the odd synchronization table at the end of the
static segment of an odd communication cycle, the FlexRay module will not
update the values SFODB and SFODA.
SFEVB
13
13
0
0
Figure 3-30. Sync Frame Table Offset Register (SFTOR)
Figure 3-29. Sync Frame Counter Register (SFCNTR)
12
12
0
0
11
11
0
0
Table 3-36. SFCNTR Field Descriptions
Additional Reset: RUN Command
10
10
0
0
SFEVA
MFR4300 Data Sheet, Rev. 3
SFT_OFFSET[15:1]
Tables”.
0
0
9
9
NOTE
0
0
8
8
Description
0
0
7
7
6
0
6
0
SFODB
0
0
5
5
(vsSyncIdListB
(vsSyncIdListA
(vsSyncIdListB
(vsSyncIdListA
0
0
4
4
0
0
3
3
Freescale Semiconductor
for odd cycle)
for odd cycle)
for even cycle)
for even cycle)
0
0
2
2
SFODA
Section 3.4.12,
Write:
POC:config
1
0
1
0
0
0
0
0
0