mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 77

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.3.2.10
This register provides the means to control some of the interrupt request lines and provides the
corresponding interrupt flags. The interrupt flags MIF, PRIF, CHIF, RBIF, and TBIF are the outcome of a
binary OR of the related individual interrupt flags and interrupt enables. The generation scheme for these
flags is depicted in
Support. These flags are cleared automatically when all of the corresponding interrupt flags or interrupt
enables in the related interrupt flag and enable registers are cleared by the application. In this register the
application can clear only the interrupt flags WUPIF, FNEBIF, and FNEAIF, by writing ‘1’ to each them.
Writing ‘0’ will not change the flag state. If the application clears a flag and the FlexRay module sets the
flag on the same cycle, then that flag remains set.
Freescale Semiconductor
0x0016
Reset
FNEBIF
WUPIF
W
Field
CHIF
R MIF
PRIF
MIF
15
13
13
12
11
15
0
PRIF CHIF
Module Interrupt Flag — This flag is set if at least one of the other interrupt flags is in this register is asserted
and the related interrupt enable is asserted, too. The FlexRay module generates the module interrupt request if
MIE is asserted.
0 No interrupt flag is asserted or no interrupt enable is set
1 At least one of the other interrupt flags in this register is asserted and the related interrupt bit is asserted, too
Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags in the
Interrupt Flag Register 0 (PIFR0)
interrupt enable flag is asserted, too. The FlexRay module generates the combined protocol interrupt request if
the PRIE flag is asserted.
0 All individual protocol interrupt flags are equal to 0 or no interrupt enable bit is set.
1 At least one of the individual protocol interrupt flags and the related interrupt enable is equal to 1.
CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the
Register (CHIERFR)
module generates the combined CHI error interrupt if the CHIE flag is asserted, too.
0 All CHI error flags are equal to 0 or the chi error interrupt is disabled
1 At least one CHI error flag is asserted and chi error interrupt is enabled
Wakeup Interrupt Flag — This flag is set when the FlexRay module has received a wakeup symbol on the
FlexRay bus. The application can determine on which channel the wakeup symbol was received by reading the
related wakeup flags WUB and WUA in the
the wakeup interrupt request if the WUPIE flag is asserted.
0 No wakeup condition or interrupt disabled
1 Wakeup symbol received on FlexRay bus and interrupt enabled
Receive FIFO channel B Not Empty Interrupt Flag — This flag is set when the receive FIFO for channel B is
not empty. If the application writes 1 to this bit, the FlexRay module updates the FIFO status, increments or wraps
the FIFO read index in the
FIFO B is now empty. If the FIFO is still not empty, the FlexRay module sets this flag again. The FlexRay module
generates the Receive FIFO B Not empty interrupt if the FNEBIE flag is asserted.
0 Receive FIFO B is empty or interrupt is disabled
1 Receive FIFO B is not empty and interrupt enabled
Global Interrupt Flag and Enable Register (GIFER)
14
0
Figure
13
0
Figure 3-9. Global Interrupt Flag and Enable Register (GIFER)
3-141. For more details on interrupt generation, see
12
0
Table 3-16. GIFER Field Descriptions (Sheet 1 of 3)
is asserted and the chi error interrupt enable GIFER.CHIE is asserted. The FlexRay
11
0
Receive FIFO B Read Index Register (RFBRIR)
10
0
MFR4300 Data Sheet, Rev. 3
and
RBIF
Protocol Interrupt Flag Register 1 (PIFR1)
0
9
Protocol Status Register 3 (PSR3).
TBIF
0
8
Description
MIE
0
7
PRIE CHIE
6
0
0
5
and clears the interrupt flag if the
0
4
The FlexRay module generates
Section 3.4.19, “Interrupt
FlexRay Module (FLEXRAYV2)
is asserted and the related
0
3
CHI Error Flag
Write: Normal Mode
0
2
RBIE TBIE
1
0
Protocol
0
0
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