mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 67

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.3.2.2
This section describes the write access restriction terms that apply to all registers.
3.3.2.2.1
For each register bit and register field, the write access conditions are specified in the detailed register
description. A description of the write access conditions is given in
or field, none of the given write access conditions is fulfilled, any write attempt to this register bit or field
is ignored without any notification. The values of the bits or fields are not changed. The condition term [A
or B] indicates that the register or field can be written to if at least one of the conditions is fulfilled.
3.3.2.2.2
For some of the registers, a 16-bit wide write access is required to ensure correct operation. This write
access requirement is stated in the detailed register description for each register affected
3.3.2.2.3
The following memory mapped registers are used to access multiple internal registers.
Each of these memory mapped registers provides a SEL field and a WMD bit. The SEL field is used to
select the internal register. The WMD bit controls the write mode. If the WMD bit is set to ‘0’ during the
write access, all fields of the internal register are updated. If the WMD bit set to ‘1’, only the SEL field is
Freescale Semiconductor
Protocol RUN Command
Message Buffer Disable
Any Time
Disabled Mode
Normal Mode
POC:config
MB_DIS
MB_LCK
Condition
•
•
•
•
Strobe Signal Control Register (STBSCR)
Slot Status Selection Register (SSSR)
Slot Status Counter Condition Register (SSCCR)
Receive Shadow Buffer Index Register (RSBIR)
Condition
Register Write Access
Register Write Access Restriction
Register Write Access Requirements
Internal Register Access
PSR0.PROTSTATE =
MBCCSRn.LCKS = ‘1’
MBCCSRn.EDS = ‘0’
MCR.MEN = ‘0’
MCR.MEN = ‘1’
Indication
Table 3-5. Additional Register Reset Conditions
Table 3-6. Register Write Access Restrictions
The register field is reset when the application writes to RUN command “0101” to the
POCCMD field in the
The register field is reset when the application has disabled the message buffer.
This happens when the application writes ‘1’ to the message buffer disable trigger bit
MBCCSRn.EDT while the message buffer is enabled (MBCCSn.EDS = 1) and the FlexRay
module grants the disable to the application by clearing the MBCCSRn.EDS bit.
-
POC:config
MFR4300 Data Sheet, Rev. 3
Protocol Operation Control Register
No write access restriction.
Write access only when the FlexRay module is in Disabled Mode.
Write access only when the FlexRay module is in Normal Mode.
Write access only when the Protocol is in the
Write access only when the related Message Buffer is disabled.
Write access only when the related Message Buffer is locked.
Description
Table
Description
3-6. If, for a specific register bit
(POCR).
FlexRay Module (FLEXRAYV2)
POC:config
state.
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