mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 84

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

FlexRay Module (FLEXRAYV2)
This register defines whether the interrupt flags defined in
generate a interrupt request.
3.3.2.15
This register holds the CHI related error flags. The application can clear any error flag by writing a '1' to
it. Writing a ‘0’ will not change the state of the flag. If the application clears a flag while the FlexRay
module sets the flag at the same time, then that flag remains set. The interrupt generation for each of these
error flags is controlled by the CHI interrupt enable bit CHIE in the
Register
84
0x0020
Reset
SSI[3:0]_IE
PECF_IE
EMC_IE
PSC_IE
ODT_IE
EVT_IE
IPC_IE
W
Field
11–8
R
15
14
13
12
5
4
15
0
(GIFER).
Error Mode Changed Interrupt Enable — This bit controls EMC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Illegal Protocol Control Command Interrupt Enable — This bit controls IPC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Protocol Engine Communication Failure Interrupt Enable — This bit controls PECF_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Protocol State Changed Interrupt Enable — This bit controls PSC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Slot Status Counter Incremented Interrupt Enable — This bit controls SSI[3:0]_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Even Cycle Table Written Interrupt Enable — This bit controls EVT_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Odd Cycle Table Written Interrupt Enable — This bit controls ODT_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
CHI Error Flag Register (CHIERFR)
14
0
13
0
12
0
Figure 3-14. CHI Error Flag Register (CHIERFR)
11
0
Table 3-20. PIER1 Field Descriptions
10
0
MFR4300 Data Sheet, Rev. 3
0
9
0
8
Description
0
7
Protocol Interrupt Flag Register 1 (PIFR1)
6
0
Global Interrupt Flag and Enable
0
5
0
4
0
3
Freescale Semiconductor
Write: Normal Mode
0
2
1
0
can
0
0