mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 78

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

FlexRay Module (FLEXRAYV2)
78
FNEAIF
FNEBIE
FNEAIE
WUPIE
Field
PRIE
CHIE
RBIF
TBIF
MIE
10
9
8
7
6
5
4
3
2
Receive FIFO channel A Not Empty Interrupt Flag — This flag is set when the receive FIFO for channel A is
not empty. If the application writes 1 to this bit, the FlexRay module updates the FIFO status, increments or wraps
the FIFO read index in the
FIFO A is now empty. If the FIFO is still not empty, the FlexRay module sets this flag again. The FlexRay module
generates the Receive FIFO A Not empty interrupt if the FNEAIE flag is asserted.
0 Receive FIFO A is empty or interrupt is disabled
1 Receive FIFO A is not empty and interrupt enabled
Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive message
buffers (MBCCSn.MTD = 0) both the interrupt flag MBIF and the interrupt enable bit MBIE in the corresponding
Message Buffer Configuration, Control, Status Registers (MBCCSRn)
clear this RBIF flag directly. This flag is cleared by the FlexRay module when all of the interrupt flags MBIF of
the individual receive message buffers are cleared by the application or if the application has cleared the
interrupt enables bit MBIE.
0 None of the individual receive message buffers has the MBIF and MBIE flag asserted.
1 At least one individual receive message buffer has the MBIF and MBIE flag asserted.
Transmit Buffer Interrupt Flag — This flag is set if for at least one of the individual single or double transmit
message buffers (MBCCSn.MTD = 0) both the interrupt flag MBIF and the interrupt enable bit MBIE in the
corresponding
application can not clear this TBIF flag directly. This flag is cleared by the FlexRay module when either all of the
individual interrupt flags MBIF of the individual transmit message buffers are cleared by the application or the
host has cleared the interrupt enables bit MBIE.
0 None of the individual transmit message buffers has the MBIF and MBIE flag asserted.
1 At least one individual transmit message buffer has the MBIF and MBIE flag asserted.
Module Interrupt Enable — This flag controls if the module interrupt line is asserted when the MIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
Protocol Interrupt Enable — This flag controls if the protocol interrupt line is asserted when the PRIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
CHI Interrupt Enable — This flag controls if the CHI interrupt line is asserted when the CHIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
Wakeup Interrupt Enable — This flag controls if the wakeup interrupt line is asserted when the WUPIF flag is
set.
0 Disable interrupt line
1 Enable interrupt line
Receive FIFO channel B Not Empty Interrupt Enable — This flag controls if the receive FIFO B interrupt line
is asserted when the FNEBIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
Receive FIFO channel A Not Empty Interrupt Enable — This flag controls if the receive FIFO A interrupt line
is asserted when the FNEAIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
Message Buffer Configuration, Control, Status Registers (MBCCSRn)
Table 3-16. GIFER Field Descriptions (Sheet 2 of 3)
Receive FIFO A Read Index Register (RFARIR)
MFR4300 Data Sheet, Rev. 3
Description
are asserted. The application can not
and clears the interrupt flag if the
Freescale Semiconductor
are equal to ‘1’. The