mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 97

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

This register provides five combined interrupt flags and a copy of three individual interrupt flags. The
combined interrupt flags are the result of a binary OR of the values of other interrupt flags regardless of
the state of the interrupt enable bits. The generation scheme for the combined interrupt flags is depicted in
Figure
flags in the
application interrupt flag check. To clear the individual interrupt flags, the application must use the
Interrupt Flag and Enable Register
Freescale Semiconductor
FNEBIF
FNEAIF
WUPIF
Field
CHIF
PRIF
RBIF
TBIF
MIF
7
6
5
4
3
2
1
0
3-143. The individual interrupt flags WUPIF, FNEBIF, and FNEAIF are copies of corresponding
Global Interrupt Flag and Enable Register (GIFER)
Module Interrupt Flag — This flag is set if there is at least one interrupt source that has its interrupt flag
asserted.
0 No interrupt source has its interrupt flag asserted
1 At least one interrupt source has its interrupt flag asserted
Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags in the
Interrupt Flag Register 0 (PIFR0)
0 All individual protocol interrupt flags are equal to 0
1 At least one of the individual protocol interrupt flags is equal to 1
CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the
Register (CHIERFR)
0 All CHI error flags are equal to 0
1 At least one CHI error flag is equal to 1
Wakeup Interrupt Flag — Copy of GIFER.WUPIF
Receive FIFO channel B Not Empty Interrupt Flag — Copy of GIFER.FNEBIF
Receive FIFO channel A Not Empty Interrupt Flag — Copy of GIFER.FNEAIF
Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive message
buffers (MBCCSn.MTD = 0) the interrupt flag MBIF in the corresponding
Control, Status Registers (MBCCSRn)
0 None of the individual receive message buffers has the MBIF flag asserted.
1 At least one individual receive message buffers has the MBIF flag asserted.
Transmit Message Buffer Interrupt Flag — This flag is set if for at least one of the individual single or double
transmit message buffers (MBCCSn.MTD = 1) the interrupt flag MBIF in the corresponding
Configuration, Control, Status Registers (MBCCSRn)
0 None of the individual transmit message buffers has the MBIF flag asserted.
1 At least one individual transmit message buffers has the MBIF flag asserted.
The meanings of the five combined status bits MIF, PRIF, CHIF, RBIF, and
TBIF are different from those mentioned in the
Enable Register
is equal to 1.
(GIFER).
Table 3-35. CIFRR Field Descriptions
(GIFER).
MFR4300 Data Sheet, Rev. 3
or
Protocol Interrupt Flag Register 1 (PIFR1)
is equal to 1.
NOTE
Description
is equal to 1.
Global Interrupt Flag and
and are provided here to simplify the
Message Buffer Configuration,
FlexRay Module (FLEXRAYV2)
is equal to 1.
CHI Error Flag
Message Buffer
Protocol
Global
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