mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 222

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Clocks and Reset Generator (CRG)
6.2
Table 6-1
6.3
6.3.1
222
1
2
3
Address in MFR4300 = 0x00E0
Reset
TXD_BG[1:2]/IF_SEL[1:0]
CHICLK_CC
CLKOUT/TM0
RESET#
INT_CC#
TEST
DBG[3:2]/CLK_S[1:0]
EXTAL/CLK_CC
XTAL
# – signal is active-low
Acronyms:
PC – (Pullup/pulldown Controlled) Register controlled internal weak pullup/pulldown for a pin in the input mode
PD – (Pulldown) Internal weak pulldown for a pin in the input mode
DC – (Drive strength Controlled) Register controlled drive strength for a pin in the output mode
Z – Tristated pin
Reset state: All pins with the PC option – pullup/pulldown is disabled,
all pins with the DC option – have full drive strength
W
Field
CMIE
R
0
15
Pin Name
0
0
MFR4300 Relevant Pins for the CRG
CRG Registers
describes the MFR4300 pins relevant for the CRG block.
Detection Enable Register (DER)
Clock Monitor Mechanism Enable
0 Range filter disabled
1 Range filter enabled
14
0
0
1
13
0
0
12
0
0
In/Out Pin type
I/O
I/O
I/O
O
I
I
I
I
I
Table 6-1. MFR4300 Relevant Pins for the CRG
Figure 6-1. Detection Enable Register (DER)
11
0
0
Table 6-2. DER Field Descriptions
OD/DC
DC/PD
DC/PD
DC
PD
-
-
-
-
10
0
0
MFR4300 Data Sheet, Rev. 3
2,3
PHY Data transmitter output / Host interface select
External CHI clock input – selectable
Controller clock output–selectable between disabled, 4/10/40 MHz/ Test
mode selection for production testing only
Hardware reset input
Controller interrupt output
Factory Test mode select– should be tied to logic low in application
Debug strobe point / Output clock select
Crystal driver / External clock pin
Crystal driver pin
0
0
9
0
0
8
Description
0
0
7
6
0
0
Functional Description
0
0
5
0
0
4
0
0
3
Freescale Semiconductor
0
0
2
Write: Any Time
1
0
0
CMIE
0
0