mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 30

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Device Overview
Features specific to the MFR4300 include the following:
2.2.1
2.2.1.1
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— One receive FIFO per channel
— Up to 256 entries for each FIFO
— Global frame ID filtering, based on both value/mask filters and range filters
— Global channel ID filtering
— Global message ID filtering for the dynamic segment
Four configurable slot error counters
Four dedicated slot status indicators
— Used to observe slots without using receive message buffers
Provides measured value indicators for clock synchronization
— PE internal synchronization frame ID and measurement tables can be copied into the FlexRay
Fractional macroticks are supported for clock correction
Maskable interrupt sources provided through individual and combined interrupt lines
One absolute timer
One timer that can be configured to absolute or relative
Two hardware selectable host interfaces:
— HCS12 Interface for direct connection to Freescale’s HCS12 family of microcontrollers, with
— Asynchronous Memory Interface (AMI) for asynchronous connection to microcontrollers —
— 8K bytes addressable for byte or word accesses
Internal quartz oscillator of 40 MHz
CHI and AMI clock selectable between 40 MHz oscillator clock used for PE and 20 MHz to
80 MHz separate CHI/AMI-only clock
Internal voltage regulator for the digital logic and the oscillator
Hardware selectable clock output to drive external host devices: disabled, 4, 10, or 40 MHz
Maskable interrupt sources available over one interrupt output line
Electrical physical layer interface compatible with dedicated FlexRay physical layer
Four multiplexed debug strobe pins
The duration of a microtick (µT) is one CLK_CC period (25 ns at 40 MHz).
A microtick starts with the rising edge of CLK_CC.
memory
interface clock signal to synchronize the data transfer (the maximum frequency of this clock
signal can be calculated from the ECLK pulse width low and high times, t
in
minimum read access time of 53 ns (with CHICLK_CC running at 80 MHz)
MFR4300 Implementation Parameters and Constraints
Implementation Parameters
Table
A-14.)
MFR4300 Data Sheet, Rev. 3
Freescale Semiconductor
LEC
and t
HEC
given