mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 223

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

6.3.2
6.4
6.4.1
The CRG will provide a system reset in any of the following events: power-on, low-voltage or clock
monitor failure detected, low level detected at the RESET# pin. Entry into reset is asynchronous and does
not require a clock. However, the MFR4300 cannot sequence out of reset in Functional Mode without a
system clock.
The CRG scans, during different periods depending on the origin of the reset source, the interface type, the
AMI clock source and the CLKOUT mode selection pins: IF_SEL[1:0] and CLK_S[1:0].
Freescale Semiconductor
Address in MFR4300 = 0x00E2
Reset
CDCV
W
Field
CMIF
R
PRIF
ERIF
ECS
LVIF
10-9
0
1
2
3
8
15
0
0
Functional Description
Clock and Reset Status Register (CRSR)
Reset Generation
Low Voltage Reset Interrupt Flag — set when a low-voltage reset has occurred.
Cleared when writing a 1. Writing 0 has no effect.
Clock Monitor Reset Interrupt Flag — set when a clock-monitor reset has occurred.
Cleared when writing a 1. Writing 0 has no effect.
Note: If LVIF bit or PRIF bit is set to 1 then the CMIF bit value is 0.
Power-on Reset Interrupt Flag — set when a power-on reset has occurred.
Cleared when writing a 1. Writing 0 has no effect.
External Reset Interrupt Flag — set when a external reset has occurred.
Cleared when writing a 1. Writing 0 has no effect.
Note: If LVIF bit or PRIF bit is set to 1 then the ERIF bit value is “0“.
CHI and host interface Clock Source
0 CHI and host interface are clocked by EXTAL/CLK_CC
1 CHI and host interface are clocked by CHICLK_CC
CLKOUT Division Control Value — contains sampled value of CLK_S[1:0]. The CRG writes this value after a
power-on, low-voltage or clock monitor reset, according to the values sampled on the CLK_S[1:0] pins.
See
14
Table 6-4
0
0
On a power-on or low-voltage reset, CMIF and PRIF are both cleared to “0“.
Table 2-5
13
0
0
depicts reset sources priorities.
for coding.
After reset, the clock monitor mechanism is disabled.
12
0
0
Figure 6-2. Clock and Reset Status Register (CRSR)
11
0
0
Table 6-3. CRSR Field Descriptions
10
0
MFR4300 Data Sheet, Rev. 3
CDCV
0
9
NOTE
NOTE
ECS
0
8
Description
0
0
7
6
0
0
0
0
5
0
0
4
Clocks and Reset Generator (CRG)
ERIF PRIF CMIF
0
3
0
2
Write: Any Time
1
0
LVIF
0
0
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