mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 228

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Clocks and Reset Generator (CRG)
Next table shows the interface selection encoding provided by the CRSR.ECS bit:
If, after the evaluation, the IF_SEL[1:0] are both high, the CRG sets to 1 the CRSR.ECS bit; otherwise the
CRG resets that bit.
6.4.3
The CLKOUT mode selection is done when the DBG[3:2]/CLK_S[1:0] pins are in the CLK_S[1:0] mode.
In the DBG[3:2] modes the pads are outputs from the MFR4300 device.
The CLKOUT mode selection is made upon the levels of the CLK_S[1:0] signals in the latching window
while a power-on, low voltage, clock monitor or external reset process is ongoing. The CRG latches the
CLK_S[1:0] signal values during the latching window as presented on
Figure
228
6-11. The latched values are indicated in the CRSR.CDCV field.
IF_SEL[0;1]
CLKOUT Mode Selection and Control
RESET#
The PIM block selects the DBG[3:2]/CLK_S[1:0] pads modes based on the
system reset signal.
Figure 6-8. Interface Selection during External Reset
Table 6-5. IF_SEL[1:0] Encoding by CRSR.ECS
IF_SEL1
1
0
1
MFR4300 Data Sheet, Rev. 3
~30 EXTAL/CLK_CC periods
IF_SEL0
NOTE
~60 EXTAL/CLK_CC periods
0
1
1
CRSR.ECS
0
0
1
Figure
Latching window
6-9,
Figure 6-10
Freescale Semiconductor
and