mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 179

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

message buffers can be RC1-reconfigured when in the HDis or HDisLck state. Double transmit message
buffers can be RC1-reconfigured if both the transmit side and the commit side are in the HDis state.
3.4.8.1.2
A reconfiguration will not change the buffer type of the individual message buffer if the message buffer
buffer type bit MBCCSRn.MBT is not changed. This type of reconfiguration is denoted by RC2 in
Figure
message buffers can be RC2-reconfigured when in the HDis or HDisLck state.
3.4.8.1.3
A reconfiguration will change the buffer type of the individual message buffer if the message buffer type
bit MBCCSRn.MBT is changed. This type of reconfiguration is denoted by RC3 in
reconfiguration splits one double buffer into two single buffers or combines two single buffer into one
double buffer. In the later case, the two single message buffers must have consecutive message buffer
numbers and the smaller one must be even. Message Buffers can be RC3 reconfigured if they are in the
HDis state.
3.4.9
This section provides a detailed description of the two receive FIFOs.
3.4.9.1
The receive FIFOs implement the queued receive buffer defined by the FlexRay Communications System
Protocol Specification, Version 2.1. One receive FIFO is assigned to channel A, the other receive FIFO is
assigned to channel B. Both FIFOs work completely independent from each other.
The message buffer structure of each FIFO is described in
the FRM for each of the two receive FIFOs is characterized by:
Freescale Semiconductor
RC1
•
•
3-128. It applies only to single transmit and receive message buffers. Single transmit and receive
The index of the first FIFO entry given by
The number of FIFO entries and the length of each FIFO entry as given by
and Size Register (RFDSR)
Receive FIFO
Overview
Buffer Type Not Changed (RC2)
Buffer Type Changed (RC3)
single RX
Figure 3-128. Message Buffer Reconfiguration Scheme
RC3
MFR4300 Data Sheet, Rev. 3
double TX (transmit side)
double TX (commit side)
Receive FIFO Start Index Register (RFSIR)
RC1
RC2
Section 3.4.3.3, “Receive FIFO”.
RC3
single TX
FlexRay Module (FLEXRAYV2)
Figure
Receive FIFO Depth
3-128. The RC3
The area in
RC1
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