UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 134
Manufacturer Part Number
4 BIT SINGLE-CHIP MICROCOMPUTER
(2) Noise eliminator and edge detection mode register
Note When a sampling clock is
Cautions 1. Since the INT0 pin input is sampled with a clock, INT0 does not operate in a standby mode.
As shown in Fig. 5-2 and Fig. 5-3, the INT0, INT1, and INT2 pins are configured as external interrupt input
pins that enable detection edge selection.
In addition, INT0 is provided with a noise elimination function based on a sampling clock. Basically, the
noise eliminator eliminates pulses narrower than two sampling clock cycles
accept pulses wider than one sampling clock cycle as interrupt signals depending on the sampling timing.
It surely accepts pulses wider than two sampling clock cycles as interrupt signals.
INT0 has two sampling clocks
edge detection mode register (see Fig. 5-4).
The IRQ2 is set by detecting a rising edge of the INT2 pin input.
The edge detection mode registers (IM0 and IM1) used to select a detection edge have the format shown
in Fig. 5-4. A 4-bit memory manipulation instruction is used to set IM0 or IM1. A RESET input clears all
bits to 0, and a rising edge is selected for INT0, INT1, and INT2.
When a sampling clock is f
2. When INT0/P10 is used as a port, pulses input from INT0/P10 go through the noise
Set by a reference time interval signal from the basic interval timer.
Set by a detected rising or falling edge of an INT4/P00 pin input signal.
Set by a detected edge of an INT0/P10 pin input signal. The detection edge is specified
by the INT0 mode register (IM0).
Set by a detected edge of an INT1/P11 pin input signal.
by the INT1 mode register (IM1).
Set by a serial data transfer completion signal for the serial interface.
Set by a match signal from timer/event counter 0.
Set by a match signal from the timer/pulse generator.
Set by a key scan timing signal from the display controller.
Set by a signal from the clock timer.
Set by a detected rising edge of an INT2/P12 pin input signal.
eliminator. So the input pulses must be wider than two sampling clock cycles.
Table 5-2 Set Signals of Interrupt Request Flags
Set signal of interrupt request flag
, two sampling clock cycles are 2t
/64, two sampling clock cycles are 128/f
/64, either of which can be selected according to bit 3 (IM03) of the
The detection edge is specified
as noise. However, it may