UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 89

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UPD75238GJ

Manufacturer Part Number
UPD75238GJ
Description
4 BIT SINGLE-CHIP MICROCOMPUTER
Manufacturer
NEC [NEC]
Datasheet
(c) Shift register (SIO0)
Fig. 4-42 shows the configuration of peripheral hardware of shift register 0. SIO0 is an 8-bit register
which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial
clock.
Serial transfer is started by writing data to SIO0.
In send operation, data written to SIO0 is output on the serial output (SO0) or serial data bus (SB0/
SB1). In receive operation, data is read from the serial input (SI0) or SB0/SB1 into SIO0.
Data can be read from or written to SIO0 by using an 8-bit manipulation instruction.
When the RESET signal is entered during operation, the value of SIO0 is undefined. When the RESET
signal is entered in the standby mode, the value of SIO0 is preserved.
Shift operation is stopped after 8-bit send or receive operation is completed.
The timing for reading SIO0 and start of serial transfer (writing to SIO0) is as follows:
• When the serial interface operation enable/disable bit (CSIE0) = 1. However, the case where CSIE0
• When the serial clock is masked after 8-bit serial transfer
• SCK0 is high.
When reading from or writing to SIO0, make sure that SCK0 is high.
In the two-wire serial I/O mode and SBI mode, the pins specified for the data bus are used for both
input and output. Because the configuration of output pins is N-ch open-drain, write FFH in SIO0 for
devices that are to receive data.
is set to 1 after data is written to the shift register is excluded.
N-ch open-drain output
CSIM0
Shift register 0
Fig. 4-42 Peripheral Hardware of Shift Register 0
Shift clock
Internal bus
Address
comparator
D
SET
BUSY/ACK
CLK
CLR
PD75238
Q
SO0 latch
RELT
CMDT
89

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