UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 137

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

(3) Interrupt priority specification register (IPS)
The interrupt priority specification register specifies an interrupt with a higher priority from multiple
interrupts using the low-order three bits.
Bit 3, interrupt master enable flag (IME), specifies whether to disable all interrupts.
The IPS is set with a 4-bit memory manipulation instruction. Bit 3 is set with an EI instruction and reset
with a DI instruction.
When changing the low-order three bits of the IPS, interrupts must be disabled (IME = 0) beforehand.
A RESET input clears all bits to 0.
Address
FB2H
IPS3
3
IPS2
2
Fig. 5-5 Interrupt Priority Specification Register
IPS1
1
IPS0
0
High-order interrupt selection
Interrupt master enable flag (IME)
0
0
0
0
1
1
1
1
0
1
Symbol
IPS
All interrupts are disabled and no vector interrupt is
activated.
The interrupt enable flag corresponding to an interrupt
request flag controls interrupt enabling/disabling.
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
All low-order interrupt
VRQ1 (INTBT/INT4)
VRQ2 (INT0)
VRQ3 (INT1)
VRQ4 (INTCSI0)
VRQ5 (INTT0)
VRQ6 (INTTPG)
VRQ7 (INTKS)
The listed vector
interrupts are treated
as high-order interrupts.
PD75238
137