UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 53

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

Address
FB7H
(4) System clock control register (SCC)
The SCC is a 4-bit register for selecting CPU clock
termination of main system clock generation with the most significant bit. (See Fig. 4-16.)
SCC.0 and SCC.3 are located at the same data memory address, but both bits cannot be changed at the
same time. Accordingly, SCC.0 and SCC.3 are set using bit manipulation instructions. SCC.0 and SCC.3
can be manipulated regardless of MBE setting.
Main system clock generation can be terminated by setting SCC.3 only when the subsystem clock is used
for operation. The STOP instruction must be used for generation termination when the main system clock
is used for operation.
A RESET input clears the SCC to 0.
Cautions 1. A time period of up to 1/f
SCC3
2. When the main system clock is used for operation, setting SCC.3 to stop clock generation
3. When SCC.3 is set to 1, the X1 input pin is connected to V
4. When the four bits of PCC are set to 0001B (
—
terminate main system clock generation, SCC.3 must be set when the machine cycles
indicated in Table 4-2 or more have elapsed after the clock is switched from the main system
clock to the subsystem clock.
does not enter the normal STOP mode.
prevent leakage in the crystal oscillator. When an external clock is used as the main system
clock, never set SCC.3 to 1.
the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other
than 0001B is set. When the system operates on the subsystem clock, the PCC bits must
also be other than 0001B.
—
Fig. 4-16 Format of the System Clock Control Register
SCC0
SCC3
Symbol
0
0
1
1
SCC
SCC0
1
0
1
0
XT
is needed to change the system clock. This means that to
Main system clock
Subsystem clock
Subsystem clock
System clock selection
with the least significant bit and for controlling the
= f
X
/16), do not set SCC.0 to 1. Before switching
Not to be set
Can oscillate
Oscillation stopped
SS
Main system clock operation
(GND electric potential) to
PD75238
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