h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 1029

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

TSR3—Timer Status Register 3
Note: * Can only be written with 0 for flag clearing.
Bit
Initial value
Read/Write
Overflow Flag
0
1
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
Input Capture/Output Compare Flag D
0
1
[Clearing conditions]
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
—
—
7
1
TGRD is functioning as input capture register
Input Capture/Output Compare Flag C
0
1
[Clearing conditions]
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while
TGRC is functioning as input capture register
—
—
6
1
Input Capture/Output Compare Flag B
0
1
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal while
TGRB is functioning as input capture register
—
—
5
0
Input Capture/Output Compare Flag A
0
1
R/(W) *
TCFV
[Clearing conditions]
• When DTC is activated by TGIA interrupt while DISEL bit
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning as output
• When TCNT value is transferred to TGRA by input capture
4
0
of MRB in DTC is 0
compare register
signal while TGRA is functioning as input capture register
Rev. 5.00 Sep 22, 2005 page 1003 of 1136
R/(W) *
TGFD
H'FE85
3
0
Appendix B Internal I/O Register
R/(W) *
TGFC
2
0
R/(W) *
TGFB
1
0
REJ09B0257-0500
R/(W) *
TGFA
0
0
TPU3