h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 452

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h8s-2646

Manufacturer Part Number
h8s-2646
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 12 Watchdog Timer
WDT0 TCSR Bit 3—Reserved Bit: It is always read as 1 and cannot be modified.
WDT1 TCSR Bit 3—Reset or NMI (RST/NMI
reset request and an NMI request when the TCNT overflows during the watchdog timer mode.
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (φ) or subclock (φ SUB), for input to TCNT.
• WDT0 Input Clock Select
Note: * An overflow period is the time interval between the start of counting up from H'00 on the
Rev. 5.00 Sep 22, 2005 page 426 of 1136
REJ09B0257-0500
Bit 3
RTS/NMI
0
1
Bit 2
CKS2
0
1
NMI
NMI
NMI
TCNT and the occurrence of a TCNT overflow.
Bit 1
CKS1
0
1
0
1
Description
NMI request.
Internal reset request.
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
Clock
φ/2 (initial value)
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
NMI
NMI
NMI): This bit is used to choose between an internal
Overflow Period * (where φ φ φ φ = 20 MHz)
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
(Initial value)

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