h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 204

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Bus Controller
7.8
7.8.1
The H8S/2646 Group has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and DTC which perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal.
The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means
of a bus request acknowledge signal. The selected bus master then takes possession of the bus and
begins its operation.
7.8.2
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master making the request. If there are bus requests
from more than one bus master, the bus request acknowledge signal is sent to the one with the
highest priority. When a bus master receives the bus request acknowledge signal, it takes
possession of the bus until that signal is canceled.
The order of priority of the bus masters is as follows:
7.8.3
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of
the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
• If the CPU is in sleep mode, it transfers the bus immediately.
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discrete operations, as in the case of a longword-size access, the bus is not transferred between
the operations. See appendix A.5, Bus States During Instruction Execution, for timings at
which the bus is not transferred.
Bus Arbitration
Overview
Operation
(High)
Bus Transfer Timing
DTC
>
CPU
(Low)