h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 199

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle.
Figure 7.15 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
CS * (area A)
CS * (area B)
Note: * The CS signal is generated externally rather than inside the LSI device.
Address bus
Data bus
RD
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
Figure 7.15 Example of Idle Cycle Operation (1)
T
2
T
Long output
floating time
3
Bus cycle B
T
1
T
2
Data
collision
CS * (area A)
CS * (area B)
Address bus
Data bus
Rev. 5.00 Sep 22, 2005 page 173 of 1136
RD
T
1
(b) Idle cycle inserted
Bus cycle A
(Initial value ICIS1 = 1)
T
2
Section 7 Bus Controller
T
3
REJ09B0257-0500
T
Bus cycle B
I
T
1
T
2