h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 337
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h8s-2646
Manufacturer Part Number
h8s-2646
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2646.pdf
(1165 pages)
- Current page: 337 of 1165
- Download datasheet (6Mb)
Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter
clearing source.
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
Channel
0, 3
Channel
1, 2, 4, 5
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
buffer register setting has priority, and compare match/input capture does not occur.
modified.
Bit 7
CCLR2
0
1
Bit 7
Reserved *
0
3
Bit 6
CCLR1
0
1
0
1
Bit 6
CCLR1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture *
TCNT cleared by TGRD compare match/input
capture *
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
Rev. 5.00 Sep 22, 2005 page 311 of 1136
Section 10 16-Bit Timer Pulse Unit (TPU)
2
2
1
1
1
REJ09B0257-0500
(Initial value)
(Initial value)
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