h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 791

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

22.9
22.9.1
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR (WDT1) PSS bit = 1, CPU operation shifts to subsleep mode.
In subsleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are also
stopped. The contents of the CPU’s internal registers, the data in internal RAM, and the statuses of
the internal supporting modules (excluding the SCI, ADC, HCAN, and Motor control PWM) and
I/O ports are retained.
22.9.2
Subsleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or
IRQ0 to IRQ5), or signals at the RES or STBY pins.
Exiting Subsleep Mode by Interrupts: When an interrupt occurs, subsleep mode is exited and
interrupt exception processing starts.
enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting
modules, the interrupt enable register has been set to disable the reception of that interrupt, or is
masked by the CPU.
Exiting Subsleep Mode by RES
the RES pins in section 22.6.2, Clearing Software Standby Mode.
Exiting Subsleep Mode by STBY
made to hardware standby mode.
In the case of IRQ0 to IRQ5 interrupts, subsleep mode is not cancelled if the corresponding
Subsleep Mode
Subsleep Mode
Exiting Subsleep Mode
RES: For exiting subsleep mode by the RES pins, see, Clearing with
RES
RES
STBY
STBY
STBY Pin: When the STBY pin level is driven Low, a transition is
Rev. 5.00 Sep 22, 2005 page 765 of 1136
Section 22 Power-Down Modes
REJ09B0257-0500