h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 160

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 PC Break Controller (PBC)
6.3.2
1. Initial settings
2. Satisfaction of break condition
3. Interrupt handling
6.3.3
1. The PC break interrupt is shared by channels A and B. The channel from which the request
2. The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB
3. A PC break interrupt generated when the DTC is the bus master is accepted after the bus has
Rev. 5.00 Sep 22, 2005 page 134 of 1136
REJ09B0257-0500
 Set the break address in BARA. For a PC break caused by a data access, set the target
 Set the break conditions in BCRA.
 After execution of the instruction that performs a data access on the set address, a PC break
 After priority determination by the interrupt controller, PC break interrupt exception
was issued must be determined by the interrupt handler.
after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be
requested after interrupt handling ends.
been transferred to the CPU by the bus controller.
ROM, RAM, I/O, or external address space address as the break address. Stack operations
and branch address reads are included in data accesses.
BCRA bit 6 (CDA): Select the bus master.
BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked.
BCRA bits 2, 1 (CSELA1, CSELA0): Set 01, 10, or 11 to specify data access as the break
condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
request is generated and the condition match flag (CMFA) is set.
handling is started.
PC Break Interrupt Due to Data Access
Notes on PC Break Interrupt Handling