h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 1081

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

SSR0—Serial Status Register 0
Bit
Initial value
Read/Write
Transmit Data Register Empty
0 [Clearing conditions]
1 [Setting conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
R/(W)
TDRE
7
1
*9
R/(W)
RDRF
Receive Data Register Full
6
0
0 [Clearing conditions]
1 [Setting condition]
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
When serial reception ends normally and receive data is transferred from RSR to RDR
*9
R/(W)
ORER
Overrun Error
0 [Clearing condition]
1 [Setting condition]
5
0
When the next serial reception is completed while RDRF = 1
When 0 is written in ORER after reading ORER = 1
Framing Error
*9
0 [Clearing condition]
1 [Setting condition]
When 0 is written in FER after reading FER = 1
When the SCI checks whether the stop bit at the end of the receive
data when reception ends, and the stop bit is 0
R/(W)
*8
FER
H'FF7C
4
0
*9
Parity Error
0 [Clearing condition]
1 [Setting condition]
Rev. 5.00 Sep 22, 2005 page 1055 of 1136
When 0 is written in PER after reading PER = 1
When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR
R/(W)
Transmit End
PER
0 [Clearing conditions]
1 [Setting conditions]
3
0
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
writes data to TDR
a 1-byte serial transmit character
*9
Appendix B Internal I/O Register
TEND
Multiprocessor Bit
R
2
1
0 [Clearing condition]
1 [Setting condition]
When data with a 0 multiprocessor
bit is received
When data with a 1 multiprocessor
bit is received
Multiprocessor Bit Transfer
0 Data with a 0 multi-processor
1 Data with a 1 multi-processor
bit is transmitted
bit is transmitted
*4
MPB
R
REJ09B0257-0500
1
0
*1
*2
*6
MPBT
R/W
*3
0
0
*5
SCI0
*7