h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 292
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h8s-2646
Manufacturer Part Number
h8s-2646
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2646.pdf
(1165 pages)
- Current page: 292 of 1165
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Section 9 I/O Ports
9.9.2
Table 9.16 shows the port B register configuration.
Table 9.16 Port B Registers
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to
PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior
state in software standby mode.
Rev. 5.00 Sep 22, 2005 page 266 of 1136
REJ09B0257-0500
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Port B open-drain control register
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Register Configuration
:
:
:
:
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
PB7DR
R/W
W
7
0
7
0
PB6DR
R/W
W
6
0
6
0
PB5DR
Abbreviation
PBDDR
PBDR
PBPCR
R/W
PORTB
PBODR
W
5
0
5
0
PB4DR
R/W
W
4
0
4
0
R/W
W
R/W
R
R/W
R/W
PB3DR
R/W
W
3
0
3
0
Initial Value
H'00
H'00
Undefined
H'00
H'00
PB2DR
R/W
W
2
0
2
0
PB1DR
R/W
W
1
0
1
0
Address *
H'FE3A
H'FF0A
H'FE41
H'FE48
H'FFBA
PB0DR
R/W
W
0
0
0
0
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