LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 110

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Table 4.10
4-18
Name
TESTIN
(Not available
on LSI53C875J,
LSI53C875JB)
GPIO0_
FETCH/
GPIO1_
MASTER/
Additional Interface Signals
LSI53C875JB Type Description
57, NA/74/NA
LSI53C875N,
LSI53C875J,
LSI53C875,
53/70/N5
54/71/K6
Table 4.10
Signal Descriptions
Pin No.
describes the Additional Interface Signals group.
I/O
I/O
I
Test In. When this pin is driven LOW, the LSI53C875
connects all inputs and outputs to an “AND tree.” The SCSI
control signals and data lines are not connected to the
“AND tree.” The output of the “AND tree” is connected to
the Test Out pin. This allows manufacturers to verify chip
connectivity and determine exactly which pins are not
properly attached. When the TESTIN pin is driven LOW,
internal pull-ups are enabled on all input, output, and
bidirectional pins, all outputs and bidirectional signals will
be 3-stated, and the MAC/_TESTOUT pin will be enabled.
Connectivity can be tested by driving one of the LSI53C875
pins LOW. The MAC/_TESTOUT pin should respond by
also driving LOW.
General Purpose I/O pin. Optionally, when driven LOW,
this pin indicates that the next bus request will be for an
opcode fetch. This pin powers up as a general purpose
input.
This pin has two specific purposes in the LSI Logic SDMS
software. SDMS software uses it to toggle SCSI device
LEDs, turning on the LED whenever the LSI53C875 is on
the SCSI bus. SDMS software drives this pin LOW to turn
on the LED, or drives it HIGH to turn off the LED. This
signal can also be used as data I/O for serial EEPROM
access. In this case it is used with the GPIO0 pin, which
serves as a clock, and the pin can be controlled from PCI
configuration register 0x35 or observed from the
Purpose (GPREG)
General Purpose I/O pin. Optionally, when driven LOW,
indicates that the LSI53C875 is bus master. This pin
powers up as a general purpose input.
LSI Logic SDMS software supports use of this signal in
serial EEPROM applications, when enabled, in
combination with the GPIO0 pin. When this signal is used
as a clock for serial EEPROM access, the GPIO1 pin
serves as data, and the pin is controlled from PCI
configuration register 0x35.
operating register, at address 0x07.
General