LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 125

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Register: 0x02 (0x82)
SCSI Control Two (SCNTL2)
Read/Write
SDU
CHM
SDU
7
0
Note:
CHM
6
0
Writing to this register while not connected may cause the
loss of a selection/reselection by resetting the Connected
bit.
The determination of whether the transfer is a send or
receive is made according to the value written to the I/O
bit in
self-clearing. Do not set it for low level operation.
SCSI Disconnect Unexpected
This bit is valid in the initiator mode only. When this bit is
set, the SCSI core is not expecting the SCSI bus to enter
the Bus Free phase. If it does, an unexpected disconnect
error is generated (see the Unexpected Disconnect bit in
the
During normal SCRIPTS mode operation, this bit is set
automatically whenever the SCSI core is reselected, or
successfully selects another SCSI device. The SDU bit
should be cleared with a register write (move 0x00 to
SCNTL2) before the SCSI core expects a disconnect to
occur, normally prior to sending an Abort, Abort Tag, Bus
Device Reset, Clear Queue or Release Recovery
message, or before deasserting SACK/ after receiving a
Disconnect command or Command Complete message.
Chained Mode
This bit determines whether or not the SCSI core is
programmed for chained SCSI mode. This bit is
automatically set by the Chained Block Move (CHMOV)
SCRIPTS instruction and is automatically cleared by the
Block Move SCRIPTS instruction (MOVE).
Chained mode is primarily used to transfer consecutive
wide data blocks. Using chained mode facilitates partial
receive transfers and allows correct partial send behav-
ior. When this bit is set and a data transfer ends on an
SCSI Interrupt Status Zero (SIST0)
SLPMD SLPHBEN
SCSI Output Control Latch
5
0
4
0
WSS
3
0
VUE0
(SOCL). This bit is
2
0
register, bit 2).
VUE1
1
0
WSR
0
0
5-9
7
6