LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 68

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

3.1.1.3 Memory Read
3.1.1.4 Memory Read Multiple
3.1.1.5 Memory Read Line
3.1.1.6 Memory Write
3.1.1.7 Memory Write and Invalidate
3.2 PCI Cache Mode
3.2.1 Support for PCI Cache Line Size Register
3-4
The Memory Read command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.
The Memory Read command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.
The Memory Read command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.
The Memory Write command writes data to an agent when mapped in
memory address space. All 32 address bits are decoded.
The Memory Write command writes data to an agent when mapped in
memory address space. All 32 address bits are decoded.
The LSI53C875 supports the PCI specification for an 8-bit
Size
Size
addresses corresponding to cache line boundaries. In conjunction with
the
Multiple, and Write and Invalidate are each software enabled or disabled
to allow the user full flexibility in using these commands.
The LSI53C875 supports the PCI specification for an 8-bit
Size
nonaligned addresses corresponding to cache line boundaries.
PCI Functional Description
Cache Line Size
register located in the PCI configuration space. The
register provides the ability to sense and react to nonaligned
register in PCI configuration space. It can sense and react to
register, the PCI commands Read Line, Read
Cache Line
Cache Line
Cache Line