LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 167

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

For more information on interrupts, see
Description.”
Register: 0x3A (0xBA)
Scratch Byte Register (SBR)
Read/Write
This is a general purpose register. Apart from CPU access, only register
Read/Write and Memory Moves into this register will alter its contents.
The default value of this register is zero. This register was called the
DMA Watchdog Timer on previous LSI53C8XX family products.
Register: 0x3B (0xBB)
DMA Control (DCNTL)
Read/Write
CLSE
PFF
PFEN
SSM
CLSE
7
0
PFF
6
0
Cache Line Size Enable
Setting this bit enables the LSI53C875 to sense and
react to cache line boundaries set up by the DMODE or
PCI
smaller value. Clearing this bit disables the cache line
size logic and the LSI53C875 monitors the cache line
size using the
Prefetch Flush
Setting this bit causes the prefetch unit to flush its
contents. The bit clears after the flush is complete.
Prefetch Enable
Setting this bit enables the prefetch unit if the burst size
is equal to or greater than four. For more information on
SCRIPTS instruction prefetching, see
tional Description.”
Single Step Mode
Setting this bit causes the LSI53C875 to stop after
executing each SCRIPTS instruction, and generates a
single step interrupt. When this bit is cleared, the
LSI53C875 does not stop after each instruction. It
Cache Line Size
PFEN
5
0
SSM
DMA Mode (DMODE)
4
0
register, whichever contains the
IRQM
Chapter 2, “Functional
3
0
STD
2
0
register.
Chapter 2, “Func-
IRQD
1
0
COM
0
0
5-51
7
6
5
4