LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 156

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-40
Register: 0x21 (0xA1)
Chip Test Four (CTEST4)
Read/Write
BDIS
ZMOD
ZSD
SRTM
SCSI Operating Registers
BDIS
7
0
Note:
ZMOD
6
0
To calculate the total number of bytes in both the DMA
FIFO and SCSI logic, see the section on Data Paths in
Chapter 2, “Functional Description.”
3.
Burst Disable
When set, this bit causes the LSI53C875 to perform
back-to-back cycles for all transfers. When this bit is
cleared, LSI53C875 back-to-back transfers for opcode
fetches and burst transfers for data moves are per-
formed.
High Impedance Mode
Setting this bit causes the LSI53C875 to place all output
and bidirectional pins into a high impedance state. In
order to read data out of the LSI53C875, clear this bit.
This bit is intended for board-level testing only. Do not set
this bit during normal system operation.
SCSI Data High Impedance
Setting this bit causes the LSI53C875 to place the SCSI
data bus SD[15:0] and the parity lines SDP[1:0] in a high
impedance state. In order to transfer data on the SCSI
bus, clear this bit.
Shadow Register Test Mode
Setting this bit allows access to the shadow registers
used by Memory-to-Memory Move operations. When this
bit is set, register accesses to the
Data Structure Address (DSA)
If the DMA FIFO size is set to 88 bytes, and the
result with 0x7F for a byte count between 0 and 64.
If the DMA FIFO size is set to 536 bytes, and the
result with 0x3FF for a byte count between 0 and
536.
ZSD
5
0
SRTM
4
0
MPEE
3
0
registers are directed to
Temporary (TEMP)
2
0
FBL[2:0]
0
0
0
and
7
6
5
4