LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 157

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

MPEE
FBL[2:0]
the shadow copies STEMP (Shadow TEMP) and SDSA
(Shadow DSA). The registers are shadowed to prevent
them from being overwritten during a Memory-to-Memory
Move operation. The
Temporary (TEMP)
used for table indirect calculations, and the address
pointer for a call or return instruction, respectively. This
bit is intended for manufacturing diagnostics only and
should not be set during normal operations.
Master Parity Error Enable
Setting this bit enables parity checking during master
data phases. A parity error during a bus master read is
detected by the LSI53C875. A parity error during a bus
master write is detected by the target, and the
LSI53C875 is informed of the error by the PERR/ pin
being asserted by the target. When this bit is cleared, the
LSI53C875 does not interrupt if a master parity error
occurs. This bit is cleared at power-up.
FIFO Byte Control
These bits steer the contents of the
(CTEST6)
32-bit DMA FIFO. If the FBL2 bit is set, then FBL1 and
FBL0 determine which of four byte lanes can be read or
written. When cleared, the byte lane read or written is
determined by the current contents of the
Address (DNAD)
Each of the four bytes that make up the 32-bit DMA FIFO
is accessed by writing these bits to the proper value. For
normal operation, FBL2 must equal zero.
FBL2
0
1
1
1
1
FBL1
register to the appropriate byte lane of the
0
0
0
0
x
and
FBL0
registers contain the base address
x
0
0
1
1
Data Structure Address (DSA)
DMA Byte Counter (DBC)
DMA FIFO
Byte Lane
Disabled
0
1
2
3
Chip Test Six
D[23:16]
D[31:24]
DMA Next
D[15:8]
D[7:0]
Pins
N/A
registers.
[2:0]
and
5-41
3