LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 311

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

select with SATN/ on a start sequence bit
selected bit
selection or reselection time-out bit
selection response logic test bits
semaphore bit
SFBR register
shadow register test mode bit
SI_O/ status bit
SIDL least significant byte full bit
SIDL most significant byte full bit
SIDL register
SIEN0 register
SIEN1 register
SIGP bit
single step interrupt bit
single step mode bit
single-ended operation
SIST0 register
SIST1 register
SLPAR high byte enable
SLPAR mode bit
SLPAR register
SMSG/ status bit
SOCL least significant byte full bit
SOCL register
SODL most significant byte full bit
SODL register
SODR least significant byte full bit
SODR most significant byte full bit
software reset bit
source I/O memory enable bit
SREQ/ status bit
SSEL/ status bit
SSID register
SSTAT0 register
SSTAT1 register
SSTAT2 register
stacked interrupts
start DMA operation bit
start SCSI transfer
start sequence bits
STEST0 register
STEST1 register
STEST2 register
STEST3 register
STIME0 register
STIME1 register
storage device management system (SDMS)
SWIDE register
SXFER register
synchronous clock conversion factor bits
synchronous data transfer rates
synchronous transfer period bits
T
target mode bit
TEMP register
temporary register
termination
timer test mode bit
timings
TolerANT
TolerANT enable bit
PCI
SCSI
7-50
5-32
7-51
7-7
2-23
5-54
,
5-77
5-22
5-20
5-32
5-21
5-78
5-56
5-59
5-38
5-53
5-55
5-36
5-6
5-60
5-61
5-23
5-15
,
5-22
5-64
5-66
5-26
5-27
5-29
5-70
5-72
5-73
5-75
5-10
5-22
5-23
5-32
2-32
5-57
5-38
5-8
5-76
5-4
5-75
5-51
2-19
5-24
5-52
5-10
,
Index
5-50
5-40
5-48
2-26
5-15
5-71
5-26
5-29
5-26
5-29
5-26
5-29
5-56
,
5-12
5-59
5-4
2-3
TolerANT technology
totem pole output
transfer control instructions
transfer rate
U
Ultra
Ultra SCSI
unexpected disconnect bit
W
WATN/ bit
wide SCSI
wide SCSI receive bit
wide SCSI send bit
won arbitration bit
write and invalidate enable bit
benefits
extend SREQ/SACK filtering bit
TolerANT enable bit
and SCRIPTS instruction prefetching
synchronous
Ultra enable bit
benefits
designing an Ultra SCSI system
synchronous transfer period bits
always wide SCSI bit
chained block moves
chained mode bit
enable wide SCSI bit
SWIDE register
wide SCSI receive bit
wide SCSI send bit
5-4
1-5
1-4
1-6
2-26
4-6
5-27
5-12
5-61
5-10
1-5
5-9
5-11
5-10
5-75
2-34
5-12
5-74
5-11
5-55
6-26
5-38
,
5-58
5-74
2-4
5-15
2-6
IX-7