MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 15

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

Commands
available commands. This is followed by a verbal
description of each command. Two additional Truth
Table 4:
Note 1 applies to all commands
NOTE:
Table 5:
Note 1 applies to all commands
NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
3. BA0-BA1 provide bank address and A0-A13 provide row address.
4. BA0-BA1 provide bank address; A0-Ai provide column address, (where i=9 for x16, i=9, 11 for x8, and i=9,11, 12 for x4) A10 HIGH
5. A10 LOW: BA0-BA1 determine which bank is precharged.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; for within the Self Refresh mode all inputs and I/Os are “Don’t Care” except
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts
9. DESELECT and NOP are functionally interchangeable.
1. Used to mask write data; provided coincident with the corresponding data.
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Table 4 and Table 5 provide a quick reference of
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A13 provide the op-code to
be written to the selected mode register.
enables the auto precharge feature (non persistent), and A10 LOW disables the auto precharge feature.
A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”
for CKE.
with auto precharge enabled and for write bursts.
NAME (FUNCTION)
Write Enable
Write Inhibit
Truth Table – Commands
Truth Table – DM Operation
NAME (FUNCTION)
DM
H
L
15
CS#
Tables, Table 7 on page 41, and Table 8 on page 43,
appear following the Operation section, provide cur-
rent state/next state information.
H
L
L
L
L
L
L
L
L
Valid
DQ
X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
X
H
H
H
H
L
L
L
L
CAS#
H
H
H
X
H
L
L
L
L
1Gb: x4, x8, x16
WE#
H
H
H
H
X
L
L
L
L
DDR SDRAM
Bank/Row
Bank/Col
Bank/Col
Op-Code
PRELIMINARY
ADDR
Code
X
X
X
X
©2003 Micron Technology. Inc.
NOTES
6, 7
9
9
3
4
4
8
5
2