MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 65

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active
3. NOP or COMMAND INHIBIT are the only commands allowed until after
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.
COMMAND
A0-A9, A11
BA0, BA1
during clock positive transitions.
sitions.
banks).
A12, A13
SYMBOL
t
CK (2.5)
t
CK (2)
DQS
A10
DM
t
t
DQ
t
CK#
CKE
CH
IH
CL
CK
5
5
5
1
1
1
1
F
t
t
IS
IS
NOP 2
T0
t
IH
t
IH
MIN
0.45
0.45
7.5
.90
10
ALL BANKS
ONE BANK
t
Bank(s) 4
IS
PRE
T1
t
-75
IH
CK
MAX
0.55
0.55
13
13
VALID
NOP 2
T2
Figure 44: Auto Refresh Mode
t
CH
t RP
t
CL
NOP 2
T3
UNITS
t
t
ns
ns
ns
CK
CK
T4
AR
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t RFC
t
t
t
t
RFC
t
IH
t
IS
IS
RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RFC time, CKE must be active during clock positive tran-
NOP 2, 3
Ta0
F
S
S
Ta1
AR 6
MIN
120
.90
20
1
1
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-75
1Gb: x4, x8, x16
VALID
NOP 2, 3
Tb0
MAX
DDR SDRAM
t RFC 5
PRELIMINARY
NOP 2
Tb1
©2003 Micron Technology. Inc.
DON’T CARE
UNITS
ns
ns
ns
ns
ns
Tb2
ACT
RA
RA
BA