MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 49

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

Table 14: I
0°C £ T
Notes: 1–5, 10, 12, 14; notes appear on page 54-57; See also Table 16, I
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4;
and control inputs
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
t
changing once per clock
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active
DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2;
One bank active; Address and control inputs changing once per
clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank
clock cycle;
twice per clock cycle
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT: CKE £ 0.2V
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge,
t
Active READ, or WRITE commands
RC =
CK =
CK =
t
A
t
t
CK (MIN); Address and control inputs change only during
RC (MIN);
CK (MIN);
£ +70°C; V
t
active; Address and control inputs changing once per
RC =
t
t
CK =
CK =
DD
;
t
RC (MIN);
t
t
t
t
CKE = HIGH; Address and other control inputs
DD
CK =
RC =
CK (MIN);
CK (MIN); DQ, DM, and DQS inputs changing
changing once per clock cycle
Specifications and Conditions (x4, x8)
Q = +2.5V ±0.2V, V
t
t
CK =
CK =
t
t
RAS (MAX);
CK (MIN); DQ, DM and DQS inputs
cycle. V
t
t
t
CK (MIN); CKE = LOW
CK =
CK (MIN);
I
OUT
IN
t
= 0mA
RC = minimum
t
CK (MIN); I
Reads; Continuous burst;
= V
t
CK =
REF
DD
for DQ, DQS, and DM
t
= +2.5V ±0.2V
CK (MIN); DQ, DM and
OUT
t
t
Standard
RC =
RFC = 7.8us,
t
RC allowed;
= 0mA; Address
t
RFC(MIN)
49
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
I
I
I
I
I
I
I
DD
Test Cycle Times, on page 51
I
I
DD
I
DD
I
I
DD
DD
DD
DD
DD
DD
DD
DD
DD
4W
3N
4R
5A
2P
2F
3P
0
1
5
6
7
MAX
145
180
200
210
330
485
-75
10
60
30
45
10
9
1Gb: x4, x8, x16
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DDR SDRAM
PRELIMINARY
©2003 Micron Technology. Inc.
23, 32, 50
23, 32, 50
NOTES
22, 48
22, 48
22, 48
27, 50
22, 49
51
22
22
50
11