MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 36

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MT46V128M8

Manufacturer Part Number
MT46V128M8
Description
DOUBLE DATA RATE (DDR) SDRAM
Manufacturer
MICRON [Micron Technology]
Datasheet

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NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands may be to dif-
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.
t
ferent devices, in which case
WR is referenced from the first positive CK edge after the last data-in pair.
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Bank a,
WRITE
Col b
T0
Figure 26: WRITE to PRECHARGE - Uninterrupting
t
t
t
DQSS
DQSS
DQSS
t
WR is not required and the PRECHARGE command could be applied earlier.
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
T2n
36
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR
T4
NOP
DON’T CARE
(a or all)
1Gb: x4, x8, x16
Bank,
T5
PRE
7
DDR SDRAM
TRANSITIONING DATA
t
PRELIMINARY
RP
©2003 Micron Technology. Inc.
T6
NOP

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