MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 62

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1.
2. DQ transitioning after DQS transition define
3. All DQ must transition by
4.
5.
6.
7. READ command with CL = 2 issued at T0.
1.
2.
3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
t
t
t
t
t
t
DQSCK is the DQS output window relative to CK and is the “long term” component of DQS skew.
AC is the DQ output window relative to CK, and is the “long term” component of DQ skew.
LZ (MIN) and
HZ (MAX), and
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
All DQ values, collectively
DQS, or LDQS/UDQS
DQ (Last data valid)
DQ (First data valid)
t
AC (MIN) are the first valid signal transition.
t
AC (MAX) are the latest valid signal transition.
CK#
CK
Figure 40: Data Output Timing –
3
2
t
T0
DQSQ after DQS transitions, regardless of
DQS
CK#
DM
DQ
7
CK
t LZ (MIN)
t
DQSS (MAX).
t
DQSS (MIN).
Figure 41: Data Input Timing
T0
t DQSS
3
T1
t WPRES
t
DQSQ window.
t LZ (MIN)
t RPRE
t DS
t WPRE
T1
DI
b
T2
t DSH 1
t DQSCK
t DQSCK
t DH
T2
T2
T2
62
T1n
T2n
t DQSL
1
1
t DSS 2
(MAX)
(MIN)
T2n
T2n
T2n
t AC
t
AC.
T2
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DQSH t WPST
T3
(MIN)
t DSH 1
t
T3
T3
T3
AC and
T2n
T3n
t DSS 2
DON’T CARE
TRANSITIONING DATA
T3n
T3n
T3n
t AC
T3
T4
4
t
(MAX)
DQSCK
T4
T4
T4
T4n
1Gb: x4, x8, x16
t DQSCK
t DQSCK
T4n
T4n
T4n
DDR SDRAM
T5
1
(MAX)
1
(MIN)
T5
T5
PRELIMINARY
T5
t HZ (MAX)
©2003 Micron Technology. Inc.
T5n
t HZ(MAX)
t RPST
T5n
T5n
T5n
T6