MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 37

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 8 is shown; two data elements are written.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T4 and T4n (nominal case) to register DM.
7. If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4 and T4n.
8. PRE = PRECHARGE command.
t
WR is referenced from the first positive CK edge after the last data-in pair.
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
Figure 27: WRITE to Precharge – Interrupting
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
T2n
t
WR
37
T3
NOP
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(a or all)
Bank,
T4
PRE
8
DON’T CARE
T4n
T5
NOP
1Gb: x4, x8, x16
TRANSITIONING DATA
DDR SDRAM
t
RP
PRELIMINARY
T6
©2003 Micron Technology. Inc.
NOP