MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 52

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

Table 17: Electrical Characteristics and Recommended AC Operating Conditions
0°C £ T
Notes: 1–5, 14–17, 33, notes appear on page 54-57
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (slew rate ³ 1V/ns)
Address and control input setup time (slew rate ³ 1V/ns)
Address and control input hold time (slew rate @ 0.5V/ns)
Address and control input setup time (slew rate @ 0.5V/ns)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data Hold Skew Factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window (DVW)
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to V
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
A
£ +70°C; V
DD
Q = +2.5V ±0.2V, V
DD
DD
= +2.5V ±0.2V
CL=2.5
CL=2
52
SYMBOL
t
t
t
CK (2.5)
t
t
t
t
t
DQSCK
WPRES
t
t
t
t
t
t
t
t
CK (2)
DQSQ
t
t
DQSH
WPRE
DIPW
DQSL
DQSS
t
t
t
t
t
WPST
t
t
XSNR
XSRD
t
t
t
MRD
t
RPRE
RPST
t
REFC
t
WTR
t
t
t
QHS
N/A
t
t
t
DSH
t
t
IPW
RAS
RAP
t
RCD
RRD
REFI
VTD
t
DSS
t
t
t
RFC
t
WR
DH
IH
IH
QH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
AC
CH
HP
HZ
DS
IS
IS
RC
RP
CL
LZ
F
S
F
S
t
CH,
-
127.5
-0.75
-0.75
-0.75
MIN
0.45
0.45
1.75
0.35
0.35
0.75
t
0.25
t
120
200
7.5
0.5
0.5
0.2
0.2
.90
.90
2.2
QHS
0.9
0.4
0.4
10
15
40
20
65
20
20
15
15
HP
1
1
0
1
0
t
QH -
t
CL
-75
t
DQSQ
120,000
MAX
+0.75
+0.75
+0.75
0.55
0.55
1.25
0.75
70.3
0.5
1.1
0.6
0.6
7.8
13
13
1Gb: x4, x8, x16
DDR SDRAM
UNITS
t
t
t
t
t
t
t
t
t
t
t
t
t
PRELIMINARY
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
ns
CK
ns
CK
ns
µs
µs
ns
ns
CK
©2003 Micron Technology. Inc.
NOTES
45, 52
45, 52
26, 31
26, 31
25, 26
25, 26
20, 21
18,42
18,43
30
30
31
34
14
14
35
50
42
19
25
23
23