MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 68

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MT46V128M8

Manufacturer Part Number
MT46V128M8
Description
DOUBLE DATA RATE (DDR) SDRAM
Manufacturer
MICRON [Micron Technology]
Datasheet

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NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. DOn = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The READ command can only be applied at T3 if
7.
8. Refer to Figure 38 on page 60, Figure 39 on page 61, and Figure 40 on page 62 for detailed DQS and DQ timing.
x4: A0-A9, A11, A12
t
x16: A11, A12, A13
RP starts only after
x8: A0-A9, A11
x8: A12, A13
COMMAND
x16: A0-A9
BA0, BA1
Case 1:
Case 2:
x4: A13
DQS
DQ
DQS
DQ
CK#
CKE
A10
DM
CK
1
1
4
t
t
AC (MIN) and
AC (MAX) and
t
t
IS
IS
t
NOP 5
RAS has been satisfied.
T0
t
t
IH
t
IH
DQSCK (MIN)
t
DQSCK (MAX)
Figure 47: Bank Read - With Auto Precharge
IS
Bank x
t
IS
ACT
T1
RA
RA
RA
t
IH
IH
t
CK
t
t
RCD,
RAS
t
RC
NOP 5
T2
t
RAP 6
t
CH
t
RAP is satisfied at T3.
t
CL
t
READ 2,6
IS
Bank x
3
Col n
T3
t
IH
CL = 2
68
t
LZ
(MIN)
NOP 5
T4
t
RPRE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
LZ (MIN)
t
RPRE
NOP 5
T5
t
DQSCK (MIN)
DO
t
n
DQSCK (MAX)
t
AC (MIN)
DO
t
n
AC (MAX)
T5n
t
RP 7
NOP 5
T6
1Gb: x4, x8, x16
t
HZ (MAX)
T6n
t
RPST
t
DDR SDRAM
RPST
NOP 5
T7
PRELIMINARY
TRANSITIONING DATA
DON’T CARE
©2003 Micron Technology. Inc.
Bank x
T8
ACT
RA
RA
RA

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