MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 66

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. Clock must be stable until after the self refresh command has been registered. A change in clock frequency is
2. NOPs are interchangeable with DESELECT commands, AR = AUTO REFRESH command.
3. Auto Refresh is not required at this point, but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5.
6.
7. As a general rule, any time Self Refresh Mode is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
allowed before Ta0, provided it is within the specified
self refresh mode. That is, the clock must be cycling within specifications by Ta0.
t
Tb1.
t
been refreshed via the Auto Refresh command at the distributed refresh rate,
is allowed. Self Refresh Mode may be re-entered anytime after exiting, if the following conditions are all met:
a. The DRAM had been in the Self Refresh Mode for a minimum of 200ms prior to exiting.
b.
c. At least two Auto Refresh commands are performed during each
XSNR is required before any non-READ command can be applied. That is only NOP or DESELECT commands are allowed until
XSRD (200 cycles of a valid CK and CKE = high) is required before any READ command can be applied.
SYMBOL
t
COMMAND
CK (2.5)
t
CK (2)
t
Refresh mode.
t
t
XSNR and
t
t
IH
CH
CL
IS
ADDR
F
F
DQS
CK#
CK
CKE
DM
DQ
1
2
t
RP
t
t
4
IS
t
IS
XSRD are not violated.
NOP
T0
Enter Self Refresh Mode
t
t
IH
MIN
IH
0.45
0.45
t
7.5
.90
.90
CH
10
t
CL
t
-75
IS
T1
AR
1
MAX
0.55
0.55
13
13
Figure 45: Self Refresh Mode
7
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UNITS
t
t
CK
CK
ns
ns
ns
ns
Ta0
1
Exit Self Refresh Mode
t
CK limits. Regardless, the clock must be stable before exiting
t CK
66
t IS
NOP
Ta1
SYMBOL
t
t
XSNR
XSRD
t
t
t
t
t XSNR
RFC
t
IH
IS
RP
XSRD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
S
REFI interval while the DRAM remains out of Self
S
5
6
7
Ta2
NOP
t
REFI, or faster. However, the following exception
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MIN
120
200
20
1
1
t
VALID 3
IS
VALID
Tb1
t
IH
-75
1Gb: x4, x8, x16
MAX
DDR SDRAM
VALID
Tb2
VALID
PRELIMINARY
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©2003 Micron Technology. Inc.
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DON’T CARE
VALID
VALID
Tc1
UNITS
t
ns
ns
ns
ns
ns
CK