MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 71

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. DIn = data-in from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. See Figure 41, ”Data Input Timing,” on page 62 for detailed DQ timing.
x4: A0-A9, A11, A12
x16: A11, A12, A13
SYMBOL
t
CK (2.5)
t
t
t
t
CK (2)
DQSH
DQSL
DQSS
x8: A0-A9, A11
t
t
t
t
t
DSS
CH
DH
DS
CL
x8: A21, A13
COMMAND
x16: A0-A9
BA0, BA1
x4: A13
DQS
DQ
CK#
CKE
A10
DM
CK
1
5
MIN
0.45
0.45
0.35
0.35
0.75
7.5
0.5
0.5
0.2
t
t
10
IS
IS
NOP 6
T0
t
t
IH
IH
-75
t
t
Bank x
IS
IS
ACT
T1
RA
RA
RA
MAX
0.55
0.55
1.25
13
13
t
t
IH
IH
Figure 50: Write - DM Operation
t
CK
t
t
RCD
RAS
NOP 6
T2
t
UNITS
CH
t
t
t
t
t
t
CK
CK
ns
ns
ns
ns
CK
CK
CK
CK
t
CL
WRITE 2
t
Bank x
Col n
IS
3
T3
t
t
DQSS (NOM)
IH
71
t
WPRES
t
DS
SYMBOL
t
WPRE
t
t
WPRES
t
NOP 6
T4
WPRE
t
t
WPST
t
DI
b
t
t
DSH
RAS
RCD
t
t
WR
IH
IS
RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
S
S
t
DH
T4n
t
DQSL
NOP 6
T5
t
DQSH
MIN
0.25
0.2
0.4
40
20
20
15
1
1
0
T5n
t
WPST
NOP 6
TRANSITIONING DATA
-75
T6
1Gb: x4, x8, x16
120,000
MAX
0.6
DDR SDRAM
t WR
NOP 6
T7
PRELIMINARY
©2003 Micron Technology. Inc.
DON’T CARE
UNITS
ALL BANKS
ONE BANK
Bank x 4
t
t
t
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
T8
PRE
t RP