MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 69

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. DIn = data-in. from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. See Figure 41, ”Data Input Timing,” on page 62 for detailed DQ timing.
x4: A0-A9, A11, A12
x16: A11, A12, A13
x8: A0-A9, A11
SYMBOL
t
x8: A12, A13
CK (2.5)
t
t
COMMAND
t
t
x16: A0-A9
CK (2)
DQSH
DQSL
DQSS
t
t
t
t
t
DSS
DH
CH
BA0, BA1
DS
CL
x4: A13
DQS
DQ
CK#
CKE
A10
DM
CK
1
5
t
t
IS
IS
NOP 6
T0
t
t
MIN
IH
0.45
0.45
0.35
0.35
0.75
IH
7.5
0.5
0.5
0.2
10
Figure 48: Bank Write - Without Auto Precharge
-75
t
t
Bank x
IS
IS
ACT
T1
RA
RA
RA
t
t
IH
MAX
IH
0.55
0.55
1.25
t
13
13
CK
t
t
RCD
RAS
NOP 6
T2
t
CH
UNITS
t
t
t
t
t
t
CK
CK
ns
ns
ns
ns
CK
CK
CK
CK
t
CL
WRITE 2
t
Bank x
3
Col n
IS
T3
t
t
DQSS (NOM)
IH
t
WPRES
69
t DS
t
WPRE
NOP 6
T4
DI
b
SYMBOL
t
t
WPRES
t
WPRE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WPST
t
t
t
t
t DH
DSH
t
RCD
t
RAS
t
WR
IH
IS
RP
T4n
S
S
t
DQSL
NOP 6
T5
t
DQSH
T5n
t
TRANSITIONING DATA
WPST
MIN
0.25
0.2
0.4
40
20
20
15
1
1
0
NOP 6
T6
1Gb: x4, x8, x16
-75
120,000
MAX
DDR SDRAM
0.6
t
WR
NOP 6
T7
PRELIMINARY
©2003 Micron Technology. Inc.
DON’T CARE
ALL BANKS
ONE BANK
UNITS
Bank x 4
T8
PRE
t
t
t
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
t
RP