MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 19

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

READs
shown in Figure 10 on page 20.
vided with the READ command and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst.
NOTE:
from the starting column address will be available fol-
lowing the CAS latency after the READ command.
Each subsequent data-out element will be valid nomi-
nally at the next positive or negative clock edge (i.e., at
the next crossing of CK and CK#). Figure 11 on page 21
shows general timing for each possible CAS latency
setting. DQS is driven by the DDR SDRAM along with
output data. The initial LOW state on DQS is known as
the read preamble; the LOW state coincident with the
last data-out element is known as the read postamble.
commands have been initiated, the DQs will go High-
Z. A detailed explanation of
skew),
dow are depicted in Figure 38 on page 60 and Figure 39
on page 61. A detailed explanation of
transition skew to CK) and
skew to CK) is depicted in Figure 40 on page 62.
with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data
can be maintained. The first data element from the
new burst follows either the last element of a com-
pleted burst or the last desired data element of a longer
burst which is being truncated. The new READ com-
mand should be issued x cycles after the first READ
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
READ bursts are initiated with a READ command, as
The starting column and bank addresses are pro-
During READ bursts, the valid data-out element
Upon completion of a burst, assuming no other
Data from any READ burst may be concatenated
t
QH (data-out window hold), the valid data win-
For the READ commands used in the follow-
ing illustrations, auto precharge is disabled.
t
AC (data-out transition
t
DQSQ (valid data-out
t
DQSCK (DQS
19
command, where x equals the number of desired data
element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 12 on page 22. A
READ command can be initiated on any clock cycle
following a previous READ command. Nonconsecutive
read data is shown for illustration in Figure 13 on
page 23. Full-speed random read accesses within a
page (or pages) can be performed as shown in
Figure 14 on page 24.
BURST TERMINATE command, as shown in Figure 15
on page 25. The BURST TERMINATE latency is equal
to the read (CAS) latency, i.e., the BURST TERMINATE
command should be issued x cycles after the READ
command, where x equals the number of desired data
element pairs (pairs are required by the 2n-prefetch
architecture).
truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TER-
MINATE command must be used, as shown in
Figure 16 on page 26. The
the
(
tion on WRITEs.)
a PRECHARGE command to the same bank provided
that auto precharge was not activated. The PRE-
CHARGE command should be issued x cycles after the
READ command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture). This is shown in Figure 17
on page 27. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
issued until both
part of the row precharge time is hidden during the
access of the last data elements.
t
DQSS [MIN] and
Data from any READ burst may be truncated with a
Data from any READ burst must be completed or
A READ burst may be followed by, or truncated with,
t
DQSS (MAX) case has a longer bus idle time.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RAS and
t
DQSS [MAX] are defined in the sec-
t
1Gb: x4, x8, x16
DQSS (NOM) case is shown;
t
RP has been met. Note that
DDR SDRAM
PRELIMINARY
©2003 Micron Technology. Inc.