MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 28

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

WRITEs
as shown in Figure 18.
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst and after the
t
NOTE:
will be registered on the first rising edge of DQS follow-
ing the WRITE command, and subsequent data ele-
ments will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command
and the first rising edge is known as the write pream-
ble; the LOW state on DQS following the last data-in
element is known as the write postamble.
first corresponding rising edge of DQS (
specified with a relatively wide range (from 75 per-
cent to 125 percent of one clock cycle). All of the
WRITE diagrams show the nominal case, and where
the two extreme cases (i.e.,
[MAX]) might not be intuitive, they have also been
included. Figure 19 on page 29 shows the nominal
case and the extremes of
Upon completion of a burst, assuming no other
commands have been initiated, the DQ will remain
High-Z and any additional input data will be
ignored.
with or truncated with a subsequent WRITE com-
mand. In either case, a continuous flow of input data
can be maintained. The new WRITE command can be
issued on any positive edge of clock following the pre-
vious WRITE command. The first data element from
the new burst is applied after either the last element of
a completed burst or the last desired data element of a
longer burst which is being truncated. The new WRITE
command should be issued x cycles after the first
WRITE command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture).
4. An example of nonconsecutive WRITEs is shown in
Figure 21 on page 31. Full-speed random write
accesses within a page or pages can be performed as
shown in Figure 22 on page 32.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
WR time.
WRITE bursts are initiated with a WRITE command,
The starting column and bank addresses are pro-
During WRITE bursts, the first valid data-in element
The time between the WRITE command and the
Data for any WRITE burst may be concatenated
Figure 20 on page 30 shows concatenated bursts of
For the WRITE commands used in the follow-
ing illustrations, auto precharge is disabled.
t
t
DQSS for a burst of 4.
DQSS [MIN] an d
t
DQSS) is
t
DQSS
28
sequent READ command. To follow a WRITE without
truncating the WRITE burst,
shown in Figure 23 on page 33.
subsequent READ command, as shown in Figure 24 on
page 34.
prior to the
array, and any subsequent data-in should be masked
with DM as shown in Figure 25 on page 35.
sequent PRECHARGE command. To follow a WRITE
without truncating the WRITE burst,
met as shown in Figure 26 on page 36.
subsequent PRECHARGE command, as shown in
Figure 27 on page 37 and Figure 28 on page 38. Note
that only the data-in pairs that are registered prior to
the
any subsequent data-in should be masked with DM as
shown in Figures 27 and 28. After the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until
Data for any WRITE burst may be followed by a sub-
Data for any WRITE burst may be truncated by a
Note that only the data-in pairs that are registered
Data for any WRITE burst may be followed by a sub-
Data for any WRITE burst may be truncated by a
t
WR period are written to the internal array, and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 18: WRITE Command
x4: A0–A9, A11, A12
x16: A11, A12, A13
t
WTR period are written to the internal
x8: A0–A9, A11
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
x16: A0–A9
BA0,1
CAS#
RAS#
WE#
x4: A13
x8: A13
A10
CKE
CK#
CS#
CK
t
RP is met.
1Gb: x4, x8, x16
HIGH
t
WTR should be met as
DDR SDRAM
DON’T CARE
DIS AP
EN AP
BA
CA
PRELIMINARY
©2003 Micron Technology. Inc.
t
WR should be