MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 43

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

Table 8:
(Notes: 1-6; notes appear below and on next page)
NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands
3. Current state definitions:
CURRENT STATE
Any
Idle
Row
Activating,
Active, or
Precharging
Read
(Auto-
Precharge
Disabled)
Write
(Auto-
Precharge
Disabled)
Read
(With Auto-
Precharge)
Write
(With Auto-
Precharge)
previous state was self refresh).
shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable).
Exceptions are covered in the notes below.
Idle: The bank has been precharged, and
Row Active: A row in the bank has been activated, and
ter accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Write:A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
minated
Read with Auto Precharge Enabled: See following text – 3a
Write with Auto Precharge Enabled: See following text – 3a
Truth Table – Current State Bank n - Command to Bank m
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
a. The read with auto precharge enabled or write with auto precharge enabled states can each
RAS#
be broken into two parts: the access period and the precharge period. For read with auto pre-
charge, the precharge period is defined as if the same burst was executed with auto precharge
disabled and then followed with the earliest possible PRECHARGE command that still accesses
all of the data in the burst. For write with auto precharge, the precharge period begins when
t
registration of the command and ends where the precharge period (or
H
H
H
H
H
H
H
H
H
H
H
X
X
WR ends, with
L
L
L
L
L
L
L
L
L
L
n-1
was HIGH and CKE
CAS#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
WE#
t
t
RP has been met.
WR measured as if auto precharge was disabled. The access period starts with
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
n
is HIGH (see Truth Table 2) and after
t
RCD has been met. No data bursts/accesses and no regis-
43
COMMAND/ACTION
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
XSNR has been met (if the
1Gb: x4, x8, x16
DDR SDRAM
t
RP) begins.
PRELIMINARY
©2003 Micron Technology. Inc.
NOTES
7, 9, 3a
7, 3a
7, 3a
7, 3a
7, 9
7, 8
7
7
7
7