CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet
CY8C20X34
Related parts for CY8C20X34
CY8C20X34 Summary of contents
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... PSoC CY8C20x34 TRM Technical Reference Manual (TRM) ® PSoC CY8C20x34 PSoC CY8C20x34 TRM, Version 1.0 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl.): 408.943.2600 http://www.cypress.com ...
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... Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving Cypress are committed to continuously improving the code protection features of our products. 2 PSoC CY8C20x34 TRM, Version 1.0 ...
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... Section D: System Resources 13. Digital Clocks ...................................................................................................................... 91 14. I2C Slave ........................................................................................................................... 97 15. Internal Voltage References .............................................................................................. 107 16. System Resets .................................................................................................................. 109 17. POR and LVD .................................................................................................................... 115 18. SPI ................................................................................................................................... 117 19. Programmable Timer ......................................................................................................... 131 Section E: Registers 20. Register Reference ........................................................................................................... 139 Section F: Glossary Index PSoC CY8C20x34 TRM, Version 1 135 197 213 3 ...
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... Contents Overview 4 PSoC CY8C20x34 TRM, Version 1.0 ...
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... OCD Part Pinout ........................................................................................21 Section B: PSoC Core Top-Level Core Architecture ................................................................................................................23 Core Register Summary ......................................................................................................................24 2. CPU Core (M8C) ................................................................................................................. 27 2.1 Overview ..................................................................................................................................27 2.2 Internal Registers ..................................................................................................................27 2.3 Address Spaces .....................................................................................................................27 2.4 Instruction Set Summary..........................................................................................................28 2.5 Instruction Formats ................................................................................................................30 2.5.1 One-Byte Instructions ............................................................................................30 2.5.2 Two-Byte Instructions.............................................................................................30 2.5.3 Three-Byte Instructions..........................................................................................31 2.6 Register Definitions .................................................................................................................32 2.6.1 CPU_F Register ....................................................................................................32 2.6.2 Related Registers ..................................................................................................32 PSoC CY8C20x34 TRM, Version 1.0 .................................................................................................................. ...
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... Register Definitions .................................................................................................................49 5.3.1 INT_CLR0 Registers ............................................................................................49 5.3.2 INT_MSK0 Register ..............................................................................................50 5.3.3 INT_SW_EN Register ...........................................................................................50 5.3.4 INT_VC Register ..................................................................................................51 5.3.5 Related Registers ..................................................................................................51 6 SWBootReset Function .......................................................................40 HWBootReset Function .......................................................................41 ReadBlock Function ............................................................................41 WriteBlock Function.............................................................................42 EraseBlock Function............................................................................42 ProtectBlock Function..........................................................................42 TableRead Function ...........................................................................43 EraseAll Function ................................................................................43 Checksum Function.............................................................................43 Calibrate0 Function .............................................................................43 Calibrate1 Function .............................................................................44 WriteAndVerify Function......................................................................44 PSoC CY8C20x34 TRM, Version 1.0 ...
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... Timing Diagrams ......................................................................................................................66 9.4.1 Sleep Sequence.....................................................................................................66 9.4.2 Wake Up Sequence ...............................................................................................67 9.4.3 Bandgap Refresh ...................................................................................................68 9.4.4 Watchdog Timer.....................................................................................................68 9.5 Power Modes ...........................................................................................................................69 Section C: CapSense System Top-Level CapSense Architecture .......................................................................................................71 CapSense Register Summary .............................................................................................................72 10. CapSense Module .............................................................................................................. 73 10.1 Architectural Description ..........................................................................................................73 10.1.1 Types of CapSense Approaches ...........................................................................73 10.1.1.1 10.1.2 IDAC ......................................................................................................................74 10.1.3 CapSense Counter ................................................................................................74 PSoC CY8C20x34 TRM, Version 1.0 Interrupt Modes....................................................................................56 Relaxation Oscillator............................................................................73 Contents 71 7 ...
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... Register Definitions .................................................................................................................94 13.2.1 OUT_P1 Register .................................................................................................94 13.2.2 OSC_CR0 Register 13.2.3 OSC_CR2 Register 13.2.4 Related Registers ..................................................................................................96 14. I2C Slave .......................................................................................................................... 97 14.1 Architectural Description..........................................................................................................97 14.1.1 Basic I2C Data Transfer ........................................................................................98 14.2 Application Overview ...............................................................................................................99 14.2.1 Slave Operation ....................................................................................................99 14.3 Register Definitions ...............................................................................................................100 14.3.1 I2C_CFG Register ..............................................................................................100 14.3.2 I2C_SCR Register ..............................................................................................101 8 Operation.............................................................................................75 Switch Operation .................................................................................92 ............................................................................................95 ............................................................................................96 89 PSoC CY8C20x34 TRM, Version 1.0 ...
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... SPI_CR Register .................................................................................................121 18.2.3.1 18.2.4 SPI_CFG Register ..............................................................................................122 18.2.4.1 PSoC CY8C20x34 TRM, Version 1.0 SPI Protocol Signal Definitions ..........................................................118 Usability Exceptions...........................................................................118 Block Interrupt....................................................................................118 Usability Exceptions...........................................................................119 Block Interrupt....................................................................................119 SPI Master Data Register Definitions ................................................120 SPI Slave Data Register Definitions ..................................................120 SPI Control Register Definitions ........................................................121 SPI Configuration Register Definitions ...
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... CS_CR1 .............................................................................................................154 20.3.15 CS_CR2 .............................................................................................................155 20.3.16 CS_CR3 .............................................................................................................156 20.3.17 CS_CNTL ...........................................................................................................157 20.3.18 CS_CNTH ...........................................................................................................158 20.3.19 CS_STAT ...........................................................................................................159 20.3.20 CS_TIMER .........................................................................................................160 20.3.21 CS_SLEW ..........................................................................................................161 20.3.22 PT_CFG .............................................................................................................162 20.3.23 PT_DATA1 .........................................................................................................163 20.3.24 PT_DATA0 .........................................................................................................164 20.3.25 CUR_PP .............................................................................................................165 20.3.26 STK_PP ..............................................................................................................166 20.3.27 IDX_PP ...............................................................................................................167 20.3.28 MVR_PP .............................................................................................................168 20.3.29 MVW_PP ............................................................................................................169 20.3.30 I2C_CFG ............................................................................................................170 20.3.31 I2C_SCR ............................................................................................................171 10 .............................................................137 PSoC CY8C20x34 TRM, Version 1.0 135 ...
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... Bank 1 Registers ...................................................................................................................183 20.4.1 PRTxDM0 ...........................................................................................................183 20.4.2 PRTxDM1 ...........................................................................................................184 20.4.3 SPI_CFG .............................................................................................................185 20.4.4 MUX_CRx ...........................................................................................................186 20.4.5 IO_CFG ...............................................................................................................187 20.4.6 OUT_P1 ..............................................................................................................188 20.4.7 OSC_CR0 ...........................................................................................................189 20.4.8 OSC_CR2 ...........................................................................................................190 20.4.9 VLT_CR ..............................................................................................................191 20.4.10 VLT_CMP ...........................................................................................................192 20.4.11 IMO_TR ..............................................................................................................193 20.4.12 ILO_TR ...............................................................................................................194 20.4.13 BDG_TR .............................................................................................................195 20.4.14 SLP_CFG ............................................................................................................196 Section F: Glossary Index PSoC CY8C20x34 TRM, Version 1.0 Contents 197 213 11 ...
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... Contents 12 PSoC CY8C20x34 TRM, Version 1.0 ...
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... Manual (TRM), the CY8C20x34 PSoC device does not have regular digital PSoC blocks and global interconnects that are found in most PSoC devices. The CY8C20x34 devices have one analog resource and digital logic in addition to a fast CPU, Flash program memory, and SRAM data memory to support various CapSense algorithms. ...
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... Section A: Overview Top-Level Architecture The PSoC block diagram on the next page illustrates the top-level architecture of the CY8C20x34 PSoC device. Each major grouping in the diagram is covered in this manual in its own section: PSoC Core, CapSense System, and the System Resources. Banding these three main areas together is the communication network of the system bus. ...
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... Controller 6/12 MHz Internal Main Oscillator (IMO) CAPSENSE SYSTEM Comparators SYSTEM BUS Digital I2C Clocks Slave PSoC CY8C20x34 TRM, Version 1.0 Port 3 Port 2 Port 1 Global Analog Interconnect Flash Nonvolatile Memory CPU Core (M8C) Internal Low Speed Oscillator (ILO) Multiple Clock Sources CapSense Module ...
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... This section serves as a chronicle of the PSoC Mixed-Signal Array Technical Reference Manual. PSoC Technical Reference Manual History Version/ Originator Release Date Version 1.0 VED First release of the PSoC CY8C20x34 Technical Reference Manual. This release encompasses the CY8C20x34 PSoC device. April 20, 2006 16 http://www.cypress.com. Resources include Training Seminars, Discus- http://www.cypress.com Description of Change PSoC CY8C20x34 TRM, Version 1 ...
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... C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. PSoC CY8C20x34 TRM, Version 1.0 Units of Measure This table lists the units of measure used in this manual. Units of Measure ...
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... SRAM static random access memory SROM supervisory read only memory SSADC single slope ADC SSC supervisory system call TC terminal count USB universal serial bus WDT watchdog timer WDR watchdog reset XRES external reset PSoC CY8C20x34 TRM, Version 1.0 ...
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... Pin Information This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8C20x34 PSoC device. For up-to- date ordering, pinout, and packaging information, refer to the individual PSoC device’s data sheet http://www.cypress.com/psoc. 1.1 Pinouts The CY 8C20x34 PSoC device is available in a variety of packages. Every port pin (labeled with a “P”), except for Vss, Vdd, and XRES in the following tables and illustrations, is capable of Digital IO ...
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... If not connected to ground, it should be electrically floated and not connected to any other signal. 20 CY8C20434 32-Pin PSoC Device Description AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[ P0[0 P2[6 P2[4], AI QFN 4 21 P2[2 P2[0], AI (Top View) 6 P3[2 P3[0 XRES PSoC CY8C20x34 TRM, Version 1.0 ...
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... ISSP pin which is not HiZ at POR. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. PSoC CY8C20x34 TRM, Version 1.0 CY8C20000 OCD PSoC Device NC ...
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... Pin Information 22 PSoC CY8C20x34 TRM, Version 1.0 ...
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... Section B: The PSoC Core section discusses the core components of a PSoC device with a base part number of CY8C20x34 and the registers associated with those components. The core section covers the heart of the PSoC device, which includes the M8C microcontroller; SROM, interrupt controller, GPIO, and SRAM paging; multiple clock sources such as IMO and ILO; and sleep and watchdog functionality ...
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... Page Bit CapSense Analog V Monitor CapSense Analog V Monitor ENSWINT REG_EN IOINT Freq Trim[3: PSoC CY8C20x34 TRM, Version 1.0 ...
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... An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. C Clearable register or bit(s). R Read register or bit(s). W Write register or bit(s). PSoC CY8C20x34 TRM, Version 1.0 Bit 5 Bit 4 Bit 3 SLEEP AND WATCHDOG REGISTERS (page 65) ...
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... Section B: PSoC Core 26 PSoC CY8C20x34 TRM, Version 1.0 ...
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... M8C registers are accessed using these instruc- tions: MOV A, expr MOV X, expr SWAP expr JMP LABEL PSoC CY8C20x34 TRM, Version 1.0 Register Reference chapter on page The F register is read by using address F7h in either register bank 2.3 Address Spaces The M8C has three address spaces: ROM, RAM, and regis- ters ...
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... DEC DEC [expr DEC [X+expr LCALL LJMP RETI RET JMP CALL JNZ JNC JACC INDEX Z PSoC CY8C20x34 TRM, Version 1.0 ...
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... INC Note 1 Interrupt acknowledge to Interrupt Vector table = 13 cycles. Note 2 The number of cycles required by an instruction is increased by one for instructions that span 256 byte page boundaries in the Flash memory space. PSoC CY8C20x34 TRM, Version 1.0 Instruction Format Flags INC [expr] ...
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... Two-Byte Instructions Byte 1 8-Bit Data 8-Bit Address CALL , JC , JNC , JNZ , JZ . This instruction format is used by instructions that employ the ADD used by a wide range of instructions and ADD A, [ ADD A, [X+7] ) ADD [7], A ADD [X+7 MVI A, [7] ) MVI [7], A PSoC CY8C20x34 TRM, Version 1.0 , JMP , ) ...
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... Address The first instruction format, shown in the first row of Table 2-5, is used by the LJMP and LCALL instructions. PSoC CY8C20x34 TRM, Version 1.0 These instructions change program execution uncondition- ally to an absolute address. The instructions use an 8-bit opcode, leaving room for a 16-bit destination address. ...
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... For GIE=1, the M8C samples the IRQ input for each instruc- tion. For GIE=0, the M8C ignores the IRQ. For additional information, refer to the page 179. Bit 1 Bit 0 Access Zero GIE CPU_F register on PSoC CY8C20x34 TRM, Version 1.0 ...
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... The memory address bus allows the M8C to access up to 256 bytes of SRAM, to increase the amount of available SRAM and preserve the M8C assembly language. The CY8C20x34 PSoC device has 256 bytes of SRAM with two pages of memory. To take full advantage of the paged memory architecture of the PSoC device, several registers must be used and two CPU_F register bits must be managed ...
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... Note that this ISR behavior is the default and that the PgMode bits in the CPU_F register can be changed while in an ISR. If the PgMode bits are changed while in an ISR, the pre-ISR value is still restored by the PSoC CY8C20x34 TRM, Version 1.0 ...
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... CUR_PP STK_PP Mode used by SROM functions initiated by the SSC instruction. * PSoC CY8C20x34 TRM, Version 1.0 After reset, the PgMode bits are set to 00b. In this mode, index memory accesses are forced to SRAM Page 0, just as they would PSoC device with only 256 bytes of SRAM ...
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... CUR_PP, but the address pointed to may be in another SRAM page. See the MVR_PP and MVW_PP register descriptions for more information. For additional information, refer to the CUR_PP register on page Bit 1 Bit 0 Access 24. For TMP_DRx register on Bit 1 Bit 0 Access Page Bit 165. PSoC CY8C20x34 TRM, Version 1.0 ...
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... MVW_PP register. This instruction is considered a read because data is transferred from SRAM to the microprocessor's A register (CPU_A). When an MVI A, [expr] instruction is executed in a device with more than one page of SRAM, the SRAM address that PSoC CY8C20x34 TRM, Version 1.0 Bit 5 Bit 4 Bit 3 Bit 2 the stack has grown, the program must ensure that the STK_PP value is restored when needed ...
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... User Guide for more information on the MVI [expr], A instruction. The function of this register and the MVI instructions are independent of the SRAM Paging bits in the CPU_F register. For additional information, refer to the page 169. Bit 1 Bit 0 Access Page Bit MVW_PP register on PSoC CY8C20x34 TRM, Version 1.0 ...
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... This allows the data buffer used in the supervisory operation to be located in any SRAM page. (See the RAM Paging chapter on page 33 regarding the MVR_PP and MVW_PP pointers.) PSoC CY8C20x34 TRM, Version 1.0 139. Table 4-1. List of SROM Functions Function Code 00h ...
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... The IRAMDIS bit allows the preservation of variables even if a watchdog reset (WDR) occurs. The IRAMDIS bit is reset by all system resets except watchdog reset. Therefore, this bit is only useful for watchdog resets and not general resets. PSoC CY8C20x34 TRM, Version 1.0 ...
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... ReadBlock Function ?? ?? ?? ?? ?? ?? The ReadBlock function is used to read 64 contiguous bytes ?? ?? ?? from Flash: a block. The CY8C20x34 PSoC device has Flash and therefore has 128 64-byte blocks. Valid ?? ?? ?? block IDs are 0x00 to 0x7F Table 4-6. Flash Memory Organization ?? ?? ?? 0x00 0x00 ...
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... RAM For a CPU speed of 12 MHz set to 56h. ProtectBlock Function Table 4-10 lists the protection modes available. Description In PSoC Designer Unprotected U = Unprotected Read protect F = Factory upgrade Disable external write R = Field upgrade Disable internal write W = Full protection PSoC CY8C20x34 TRM, Version 1.0 ...
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... BLOCKID 0,FAh RAM Number of Flash blocks to calculate checksum on. PSoC CY8C20x34 TRM, Version 1.0 4.1.2.8 The EraseAll function performs a series of steps that destroys the user data in the Flash banks and resets the protection block in each Flash bank to all zeros (the unpro- tected state). This function is only executed by an external programmer ...
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... KEY2 0,F9h RAM 43. Description 3Ah Stack Pointer value+3, when SSC is executed. First of 30 SRAM addresses used by this function. MVI write page pointer MVI read page pointer 42). If the verify Description 3Ah Stack Pointer value+3, when SSC is executed. PSoC CY8C20x34 TRM, Version 1.0 ...
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... CPU speed is 12 MHz. The equation for calculating the CLOCK value for an erase Flash operation is shown in Equation 3. In this equation the T has units of °C. PSoC CY8C20x34 TRM, Version 1.0 CLOCK Using the correct values for B, M, and T, in the equation above, is required to achieve the endurance specifications of the Flash ...
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... Supervisory ROM (SROM) 46 PSoC CY8C20x34 TRM, Version 1.0 ...
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... GIE is set from ‘0’ to ‘1’ in the CPU Flag register. 2. The current executing instruction finishes. 3. The internal interrupt routine executes, taking 13 cycles. During this time, these actions occur: PSoC CY8C20x34 TRM, Version 1.0 24. For a quick reference of all PSoC registers in address order, refer to 139. Figure 5-1, illustrating the concepts of posted interrupts and ...
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... Interrupt Priority 0 (Highest clocking in a ‘1’. The (Lowest) Interrupt Interrupt Name Address 0000h Reset 0004h Supply Voltage Monitor 0008h Analog 000Ch CapSense 0010h Timer 0014h GPIO 0018h SPI 001Ch I2C 0020h Sleep Timer PSoC CY8C20x34 TRM, Version 1.0 ...
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... ENSWINT is set, will cause an interrupt to post for the corre- sponding interrupt. Software interrupts can aid in debugging interrupt service routines by eliminating the need to create system level inter- actions that are sometimes necessary to create a hardware- only interrupt. PSoC CY8C20x34 TRM, Version 1.0 Bit 6 Bit 5 Bit 4 Bit 3 Sleep ...
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... INT_CLR0 register. See the INT_CLR0 register in this section for more information. For additional information, refer to the on page 176. Bit 2 Bit 1 Bit 0 Access CapSense Analog V Monitor INT_MSK0 register Bit 2 Bit 1 Bit 0 Access ENSWINT INT_SW_EN register PSoC CY8C20x34 TRM, Version 1.0 ...
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... Rather, reading 00h from the INT_VC register simply indicates that there are no pending inter- rupts. The highest priority interrupt, indicated by the value 5.3.5 Related Registers “CPU_F Register” on page 32. PSoC CY8C20x34 TRM, Version 1.0 Bit 6 Bit 5 Bit 4 Bit 3 Pending Interrupt[7:0] returned by a read of the INT_VC register, is removed from the list of pending interrupts when the M8C services an interrupt ...
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... Interrupt Controller 52 PSoC CY8C20x34 TRM, Version 1.0 ...
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... PSoC registers in address order, refer to the 6.1 Architectural Description The GPIO in the CY8C20x34 PSoC device is all uniform, except the Port 1 GPIO has stronger high drive and an option for regulated output level. These distinctions are dis- cussed in more detail in the section page 54 ...
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... Only Strong Drive mode allows for the out- puts to be driven to the regulated level. When the REG_EN bit is set high, pins configured for strong drive will drive to 3V, while those in resistive pull-up mode will drive to Vdd. PSoC CY8C20x34 TRM, Version 1.0 ...
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... INBUF (from GPIO Block Diagram Port Read PSoC CY8C20x34 TRM, Version 1.0 rupts. They are considered edge-sensitive for asserting, but level-sensitive for release of the wire-OR interrupt line GPIO interrupts are asserting, a GPIO interrupt will occur whenever a GPIO pin interrupt enable is set and the GPIO pin transitions (if not already transitioned) appropri- ately high or low to match the interrupt mode configuration ...
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... For all bypass modes, the desired drive mode of the pin must be configured separately for each pin, with the PRTxDM1 and PRTxDM0 registers. Interrupt occurs Interrupt occurs Figure 6-1 by the Alt Data PSoC CY8C20x34 TRM, Version 1.0 ...
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... Bits Interrupt Enables[7:0]. A ‘1’ enables the INTO output at the block and a ‘0’ disables INTO only High the enabled state, the type of GPIO edge that actually PSoC CY8C20x34 TRM, Version 1.0 “Summary Table of the Core Registers” on page “Summary Table of the Core Registers” on page ...
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... Bit 4 Bit 3 Bit 0: IOINT. This bit sets the GPIO Interrupt mode for all pins in the CY8C20x34 PSoC devices. GPIO interrupts are controlled at each pin by the PRTxIE registers, and also by the global GPIO bit in the INT_MSK0 register. For additional information, refer to the page 187 ...
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... Slow IMO mode is discussed further in the “Application Overview” on page 59. PSoC CY8C20x34 TRM, Version 1.0 7.2 To save power, the IMO frequency can be reduced from 12 MHz to 6 MHz using the SLIMO bit in the CPU_SCR1 regis- ter, in conjunction with the Trim values in the IMO_TR regis- ter ...
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... Slow IMO mode is used. Bits Trim[7:0]. These bits are used to trim the Inter- nal Main Oscillator. A larger value in this register increases the speed of the oscillator. For additional information, refer to the page 193. Bit 2 Bit 1 Bit 0 Access IMO_TR register on PSoC CY8C20x34 TRM, Version 1.0 ...
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... Bits 5 and 4: Bias Trim[1:0]. These bits are used to set the bias current in the PTAT Current Source. Bit 5 gets inverted, so that a medium bias is selected when both bits are ‘0’. The bias current is set according to PSoC CY8C20x34 TRM, Version 1.0 Bit 6 Bit 5 Bit 4 ...
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... Internal Low Speed Oscillator (ILO) 62 PSoC CY8C20x34 TRM, Version 1.0 ...
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... External Reset (XRES Power On Reset (POR). A WDT reset will leave the WDT enabled. Therefore, if the WDT is used in an application, all code (including initialization code) must be written as though the WDT is enabled. PSoC CY8C20x34 TRM, Version 1.0 “Summary Table of the Core Registers” on page Register Reference chapter on page 9.1.1 The Sleep Timer is a 15-bit up counter clocked by the 32 kHz clock source ...
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... The earliest the interrupt could occur is after the next instruction (write to the Sleep bit) has been executed. Therefore interrupt is pending, the sleep instruction is executed; but as described in Note 1, the sleep instruction will be ignored. The first instruction executed after the ISR is the instruction after sleep. PSoC CY8C20x34 TRM, Version 1.0 ...
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... Register” on page 61. “CPU_SCR0 Register” on page 111. “CPU_SCR1 Register” on page 110. PSoC CY8C20x34 TRM, Version 1.0 “Summary Table of the Core Registers” on page Bit 5 Bit 4 Bit 3 WDSL_Clear[7:0] the sleep timer is very close to its terminal count, the watchdog timeout will be closer to two times. To ensure a full three times timeout, both the WDT and the sleep timer may be cleared ...
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... ILO, the bandgap refresh circuit, and the sup- ply voltage monitor circuit. On the falling edge of CPU captures CPU CPUCLK asserted. responds BRQ on next The 6/12 MHz system clock with a BRA. CPUCLK edge. is halted; the Flash and bandgap are powered down. Figure 9-1. Sleep Sequence PSoC CY8C20x34 TRM, Version 1.0 ...
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... Scale) 6/12 Mhz BRQ BRA CPU PSoC CY8C20x34 TRM, Version 1 the following positive edge of the 32 kHz clock, the system-wide PD signal is negated. The Flash memory module, IMO, and bandgap any POR/LVD circuits are all powered normal operating state the next positive edge of the 32 kHz clock, the values of the bandgap are settled and sampled ...
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... In practical application important to know that the watchdog timer interval can be anywhere between two and Table 9-1. When the sleep Figure 9- “Details of Functionality for Various 114. An important aspect to remember PSoC CY8C20x34 TRM, Version 1.0 ...
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... A ILVD (LVD comparators) Table 9-4 lists example currents for N=256 and N=1024. Device leakage currents add to the totals in the table. Table 9-4. Example Currents N=256 IPOR 1 CLK32K 1 IBG 0.46 ILVD 0.4 2.9 µ A Total PSoC CY8C20x34 TRM, Version 1.0 N=1024 1 1 0.12 0.1 2.2 µ A Sleep and Watchdog 69 ...
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... Sleep and Watchdog 70 PSoC CY8C20x34 TRM, Version 1.0 ...
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... Top-Level CapSense Architecture The figure below illustrates the top-level architecture of the PSoC’s CapSense system. Each component of the figure is dis- cussed in detail in this section. CAPSENSE SYSTEM Comparators PSoC CY8C20x34 TRM, Version 1.0 CapSense System Comparators on page From IMO CapSense Module PSoC CapSense System 85 ...
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... MODE[1: INSEL[2: PXD_EN RO_EN LPF_EN[1: COLM COHM PPM # : FS_EN INTCAP[1: CMP1L CMP0L # : 00 INN0[1: CMP0R CMP0EN CPIN0 CRST0 CDS0 LUT0[3: PSoC CY8C20x34 TRM, Version 1.0 ...
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... Register Reference chapter on page 10.1 Architectural Description 10.1.1 Types of CapSense Approaches The CY8C20x34 PSoC device contains hardware support for a numbers of different capacitive sensing approaches. A block diagram of the overall capacitive sensing architecture is shown in Figure 10-1. Cs1 through Csn are the capacitors being measured ...
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... Low Byte Counter COL CO EN 8-Bit Up Counter IMO 0 CSCLK IMO/2 1 IMO/4 2 IMO/8 3 CLKSEL[1:0] Figure 10-4. CapSense Counter Block Diagram Figure 10-4) is optimized High Byte Counter CHAIN CO EN COH 8-Bit Up Counter 0 RLO CS_INT 1 To Pin 2 COLR RLOSEL 3 COHR CSOUT[1:0] PSoC CY8C20x34 TRM, Version 1.0 ...
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... Disabling and re-enabling the CapSense block will restart the timer. Relaxation Oscillator Programmable CapSense Timer Clock Register DATA[5:0] Figure 10-7. RLO Timer Block Diagram PSoC CY8C20x34 TRM, Version 1.0 Edge Detect IOW or R BLOCK_EN S IN IOW or R BLOCK_EN IMO ...
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... MODE[1:0]), the current count is held and can be subse- quently read from the counter registers. The EN bit must be toggled to ‘0’ and then back to ‘1’ to start a new count. For additional information, refer to the page 153. Bit 1 Bit 0 Access Description CS_CR0 register on PSoC CY8C20x34 TRM, Version 1.0 ...
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... Frequency of Operation 0 IDAC Sources 1 IDAC Sink Bit 4: IDAC_EN. This bit enables manual connection of the IDAC to the analog global bus. PSoC CY8C20x34 TRM, Version 1.0 Bit 5 Bit 4 Bit 3 CLKSEL[1:0] RLOSEL INV Bit 3: INV. Input Invert. When this bit is a ‘1’, the data input select is inverted. When this bit is a ‘ ...
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... The block must be stopped to read a valid value. For additional information, refer to the page 158. Bit 1 Bit 0 Access LPF_EN[1: Frequency of Operation CS_CR3 register on Bit 1 Bit 0 Access CS_CNTL register on Bit 1 Bit 0 Access CS_CNTH register on PSoC CY8C20x34 TRM, Version 1.0 ...
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... CS_TIMER Register Address Name Bit 7 Bit 6 0,A7h CS_TIMER The CapSense Timer Register (CS_TIMER) sets the timer count value. PSoC CY8C20x34 TRM, Version 1.0 Bit 5 Bit 4 Bit 3 Bit 2 COHS PPS INM COLM bit is cleared by writing a ‘0’ to this bit position. Writing a ‘1’ ...
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... Bits IDACDATA[7:0]. The 8-bit value in this register sets the current driven onto the analog global mux bus when the current DAC mode is enabled. For additional information, refer to the page 180. Bit 1 Bit 0 Access FS_EN CS_SLEW register on Bit 1 Bit 0 Access IDAC_D register on PSoC CY8C20x34 TRM, Version 1.0 ...
Page 81
... SYSCLK Block Enable Input Signal Edge Detect Count Enable Count 00 Figure 10-9. Pulse Width Frequency Timing (Mode = 01/10) SYSCLK Block Enable Count Enable Count 00 PSoC CY8C20x34 TRM, Version 1 Figure 10-8. Event Timing (Mode = 00 Figure 10-10. Continuous Timing (Mode = 11) ...
Page 82
... High Byte Count Enable High Byte Count Figure 10-11. High Byte Counter Timing (RLO clock selected) CS_TIMER[5:0] 03h (6-bit) RLO Clock EN Synchronized EN Count 00h RLO_TIMER_TC RLO_TIMER_IRQ 03h 02h 01h 00h Figure 10-12. 6-Bit RLO Timer Operation PSoC CY8C20x34 TRM, Version 1.0 ...
Page 83
... IO Analog Multiplexer This chapter explains the chip-wide IO Analog Multiplexer for the CY8C20x34 PSoC device and its associated registers. For a complete table of the IO Analog Multiplexer registers, refer to the For a quick reference of all PSoC registers in address order, refer to the 11.1 Architectural Description The CY8C20x34 PSoC device contains an enhanced ana- log multiplexer (mux) capability ...
Page 84
... IO Analog Multiplexer 11.3 Register Definitions The following registers are only associated with the Analog Bus Mux in the CY8C20x34 PSoC device and are listed in address order. For a complete table of the IO Analog Multiplexer registers, refer to the isters” on page 72. Each register description has an associated register table showing the bit structure for that register. Reg- ister bits that are grayed out throughout this document are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘ ...
Page 85
... Comparators This chapter explains the Comparators for the CY8C20x34 PSoC device and its associated registers. For a complete table of the comparator registers, refer to the PSoC registers in address order, refer to the 12.1 Architectural Description The CY8C20x34 PSoC device contains two comparators designed to support capacitive sensing or other general purpose uses ...
Page 86
... Register Definitions The following registers are only associated with the Comparators in the CY8C20x34 PSoC device and are listed in address order. For a complete table of the comparator registers, refer to the Each register description has an associated register table showing the bit structure for that register. Register bits that are grayed out throughout this document are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘ ...
Page 87
... Bit 5: CMP1R. This bit selects the input range for compara- tor 1. Setting the bit high selects a somewhat lower power mode that does not operate rail-to-rail. Bit 4: CMP1EN. This bit enables comparator 1. PSoC CY8C20x34 TRM, Version 1.0 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 88
... Bh: 1011: A .OR. B Ch: 1100: A Dh: 1101: A .OR. B Eh: 1110: A. NAND. B Fh: 1111: TRUE For additional information, refer to the page 152. Bit 2 Bit 1 Bit 0 Access CPIN0 CRST0 CDS0 CMP_CR1 register on Bit 2 Bit 1 Bit 0 Access LUT0[3: CMP_LUT register on PSoC CY8C20x34 TRM, Version 1.0 ...
Page 89
... The figure below illustrates the top-level architecture of the PSoC’s system resources. Each component of the figure is dis- cussed in detail in this section. SYSTEM BUS Digital I2C Clocks Slave PSoC CY8C20x34 TRM, Version 1.0 System Resources POR and LVD on page SPI on page 107. Programmable Timer on page Internal ...
Page 90
... EXTCLKEN IMODIS Enable Byte Transmit LRB Complete V[4: IRAMDIS # : 00 STOP # : XX VM[2: LVD PPOR Clock Clock Phase Enable # : 00 Polarity SS_EN_ Int Sel Slave One Shot START Data[4: PSoC CY8C20x34 TRM, Version 1.0 ...
Page 91
... SLEEP One of four sleep intervals may be selected from 1. second. See OSC_CR0 in the Register Definitions section of this chapter. PSoC CY8C20x34 TRM, Version 1.0 90. For a quick reference of all PSoC registers in address order, refer to the 13.1.1 The Internal Main Oscillator (IMO) is the foundation upon Figure 13-1 ...
Page 92
... SYSCLK output is then disabled after the next falling edge of SYSCLK, but before the next rising edge. This ensures a SYSCLK CPUCLK 16 32 128 256 CLK32K SLEEP Switch Operation Figure 13-2, the setting of the EXTCLKEN bit PSoC CY8C20x34 TRM, Version 1.0 ...
Page 93
... IOW EXTCLK Figure 13-3. Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One PSoC CY8C20x34 TRM, Version 1.0 In the 12 MHz case, as shown in of IOW_ and thus the setting of the EXTCLKEN bit occurs on the falling edge of SYSCLK. Since SYSCLK is already low, the output is immediately disabled ...
Page 94
... P1[0]. P10EN must be high for the sig- nal to be output on that pin. Bit 0: P10EN. This bit enables pin P1[0] for output of the signal selected by the P10D bit. For additional information, refer to the page 188. Bit 1 Bit 0 Access P10D P10EN OUT_P1 register on PSoC CY8C20x34 TRM, Version 1.0 ...
Page 95
... PSoC CY8C20x34 TRM, Version 1.0 Bit 5 Bit 4 Bit 3 No Buzz Sleep[1:0] Bits CPU Speed[2:0]. The PSoC M8C may operate over a range of CPU clock speeds M8C’s performance and power requirements to be tailored to the application. ...
Page 96
... High-Z (not High- Z analog), such as drive mode 11b with PRT1DR bit 4 set high. Bit 1: IMODIS. When set, the Internal Main Oscillator (IMO) is disabled. For additional information, refer to the page 190. Bit 1 Bit 0 Access IMODIS OSC_CR2 register on PSoC CY8C20x34 TRM, Version 1.0 ...
Page 97
... IO (input/ output) register reads and writes, and firmware synchroniza- tion will be implemented through polling and/or interrupts. PSoC CY8C20x34 TRM, Version 1.0 90. For a quick reference of all PSoC registers in address order, refer to the PSoC I2C features include: ...
Page 98
... RW direction. If the slave does not respond with an ACK for any reason, a Stop condition is generated by the master to terminate the transfer or a Restart condition may be gener- ated for a retry attempt. R/W ACK 8-Bit Data Data Transfer with 7-Bit Address Format ACK/ STOP NACK 8 9 PSoC CY8C20x34 TRM, Version 1.0 ...
Page 99
... I2C_DR register and checks for “Own Address” and R/W. PSoC CY8C20x34 TRM, Version 1.0 If there is an address match, the RW bit determines how the PSoC device will sequence the data transfer in Slave mode, as shown in the two branches of ing methodology (slave holds the SCL line low to “stall” the bus) will be used as necessary, to give the PSoC device time to respond to the events and conditions on the bus ...
Page 100
... Bit 2 Bit 1 Bit 0 Access Enable Table 14- Clock Rates /8 16 1.5 MHz/ 93.75 kHz 667 MHz/ 375 kHz 167 1.5 MHz/ 46.8 kHz 667 ns /4 PSoC CY8C20x34 TRM, Version 1.0 5.3 µ s 1.33 µ s 10.7 µ s ...
Page 101
... Under certain conditions, status is cleared automatically by the hardware. These cases are noted in There are two control bits: Transmit and ACK. These bits have RW access and may be cleared by hardware. PSoC CY8C20x34 TRM, Version 1.0 Table 14-3. Enable Operation in I2C_CFG Enable No Disabled The block is disconnected from the GPIO pins, P1[5] and P1[7] ...
Page 102
... PSoC device is unable to respond within that time, the hardware will hold the SCL line low, stalling the I2C bus. A subsequent write to the I2C_SCR register will release the stall. For additional information, refer to the page 171. PSoC CY8C20x34 TRM, Version 1.0 I2C_SCR register on ...
Page 103
... SYSCLK ENABLE BLOCK RESET RESYNC CLOCK Default 8 PSoC CY8C20x34 TRM, Version 1.0 Bit 5 Bit 4 Bit 3 Data[7:0] before writing to the I2C_SCR register, which continues the transfer. Slave Transmitter – Data bytes must be written to the I2C_DR register before the transmit bit is set in the I2C_SCR register, which continues the transfer ...
Page 104
... N=4; for 32 times sampling, N=12 derived from the half-bit rate sampling of eight and 16 clocks, respectively, minus the input latency of three (count of 4 and 12 correspond to 5 and 13 clocks). CLOCK SCL SCL_IN CLK CTR N 0 SHIFT SDA_IN SDA_OUT 104 . . . . . . . . . Figure 14-5. Basic Input/Output Timing . . . . . . . . . PSoC CY8C20x34 TRM, Version 1.0 ...
Page 105
... STOP DETECT BUS ERROR and INTERRUPT PSoC CY8C20x34 TRM, Version 1.0 Figure 14-7 shows the timing for Stop Status. This bit is set (and the interrupt occurs) two clocks after the synchronized and filtered SDA line transitions to a ‘1’, when the SCL line is high ...
Page 106
... SCL is always N-1 clocks. I/O WRITE CLOCK SCL SCL_IN (Synchronized) SDA_OUT SCL_OUT 106 14-9, firmware has until one clock after the falling edge of SCL_IN to write to the 1 Clocks No STALL STALL Figure 14-9. Slave Stall Timing “Status Tim- N-1 Clocks PSoC CY8C20x34 TRM, Version 1.0 ...
Page 107
... The connection between amplifier and capacitor is made through a CMOS switch, allowing the reference voltage to be used by the system while the refer- ence circuit is powered down. The voltage reference is trimmed to 1.30V at room temperature. 1.3V Band VREF Gap VFB = 1.3V PSoC CY8C20x34 TRM, Version 1.0 139 Figure 15-1 ...
Page 108
... The value of these bits is used to trim the bandgap refer- ence. Their value is set to the best value for the device dur- ing boot. The value of these bits should not be changed. For additional information, refer to the page 195. Bit 1 Bit 0 Access BDG_TR register on PSoC CY8C20x34 TRM, Version 1.0 ...
Page 109
... POR, XRES, and WDR the System Status and Control Register 1 (CPU_SCR1 for IRESS). Firmware can interrogate these registers to deter- mine the cause of a reset. PSoC CY8C20x34 TRM, Version 1.0 90. For a quick reference of all PSoC registers 139. 16.2 Pin Behavior During Reset ...
Page 110
... For more information on this bit, see the “SROM Function Descriptions” on page For additional information, refer to the on page 181 Sleep Clock Cycles (approximately 200 µs) R0 HiZ R0 HiZ T1 Bit 1 Bit 0 Access IRAMDIS # : 00 59). When not in external 40. CPU_SCR1 register PSoC CY8C20x34 TRM, Version 1.0 ...
Page 111
... Reset (XRES). If the bit is cleared by user code, the watchdog timer is enabled. Once cleared, the only way to reset the PORS bit through a POR or XRES. Thus, there is no way to disable the watchdog timer other than to go through a POR or XRES. PSoC CY8C20x34 TRM, Version 1.0 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 112
... CPU operation re-starts one CLK32K cycle after the n internal reset de-asserts (see How the WDR configures register reset status bits is shown in Table 16-1 on page (Stays low N=2048 16-4). 114. “Watch- for details of the Watchdog opera- Figure 16-3). 114. PSoC CY8C20x34 TRM, Version 1.0 ...
Page 113
... XRES: Reset while XRES is high (IMO off), then 7(+) cycles (IMO on), and then the CPU reset is released. CLK32 XRES Reset Sleep Timer IMO PD IMO (not to scale) CPU Reset Figure 16-4. Key Signals During POR and XRES PSoC CY8C20x34 TRM, Version 1 511 ...
Page 114
... Set PORS, Clear WDRS, Clear WDRS, Clear IRAMDIS Clear IRAMDIS On On 2.2 ms 2.2 ms XRES WDR 30 µ clock) While XRES=1 Yes All All Set PORS, Clear PORS, Clear WDRS, Set WDRS, Clear IRAMDIS IRAMDIS unchanged On On 2.2 ms 2.2 ms PSoC CY8C20x34 TRM, Version 1.0 ...
Page 115
... The three valid settings for these bits are: 00b (2.4V operation) 01b (2.7V operation) 10b (3.0V operation) PSoC CY8C20x34 TRM, Version 1.0 “Summary Table of the System Resource Registers” on page “Summary Table of the System Resource Registers” on page Bit 6 Bit 5 ...
Page 116
... This can only be meaningfully read with POR- LEV[1:0] set to disable PPOR. In that case, the PPOR sta- tus bit shows the comparator state directly. For additional information, refer to the page 192. Bit 1 Bit 0 Access LVD PPOR VLT_CMP register on PSoC CY8C20x34 TRM, Version 1.0 ...
Page 117
... Registers CONFIGURATION[7:0] CONTROL[7:0] TRANSMIT[7:0] RECEIVE[7:0] Figure 18-1. SPI Block Diagram PSoC CY8C20x34 TRM, Version 1.0 139. 18.1.1 The SPI is a Motorola™ specification for implementing full- duplex synchronous serial communication between devices. The 3-wire protocol uses both edges of the clock to enable synchronous communication without the need for stringent setup and hold requirements ...
Page 118
... When SS_ is negated, the SPIS ignores any MOSI/SCLK input from the master. In addition, the SPIS state machine is reset and the MISO output is forced to idle at logic 1. This allows for a wired-AND connection in a multi-slave environ- ment. Note that if High-Z output is required when the slave “SPIM PSoC CY8C20x34 TRM, Version 1.0 ...
Page 119
... The SPI Receive Data Register (SPI_RXR) is the SPI’s receive data register. A write to this register will clear the RX Reg Full status bit in the Control register (SPI_CR). PSoC CY8C20x34 TRM, Version 1.0 Complete (same selection as the SPIM). Mode bit 1 in the function register controls the selection. ...
Page 120
... A read from this register clears the RX Reg Full status bit in the Control register. 120 Table 18-2 explains the meaning of the Transmit and Description If a transmission is currently in progress, this register serves as a Table 18-3 explains the meaning of the Transmit and Description PSoC CY8C20x34 TRM, Version 1.0 ...
Page 121
... Read Non-inverted, clock idles low (modes 0,2) Polarity Write 1 = Inverted, clock idles high (modes 1,3) 0 Enable Read Disable SPI function. Write 1 = Enable SPI function. PSoC CY8C20x34 TRM, Version 1.0 Bit 6 Bit 5 Bit 4 Bit 3 SPI TX Reg Overrun RX Reg Full Complete Empty Bit 3: RX Reg Full. This status bit indicates a receive reg- ister full condition ...
Page 122
... Bit 0: Slave. This bit determines whether the block func- tions as a master or slave. For additional information, refer to the page 185. Description / 128 / 256 Bit 2 Bit 1 Bit 0 Access SS_EN_ Int Sel Slave SPI_CFG register on PSoC CY8C20x34 TRM, Version 1.0 ...
Page 123
... SCLK, Polarity=1 (Mode 3) MOSI MISO SS_ PSoC CY8C20x34 TRM, Version 1.0 the next data is output on the trailing edge of the clock. When the clock phase is '1', it means that the next data is output on the leading edge of the clock and that data is reg- istered as an input on the trailing edge of the clock. ...
Page 124
... When the block is disabled, the SCLK and MOSI outputs revert to their idle state. All internal state is reset (including CR0 status) to its configuration-specific reset state, except for DR0, DR1, and DR2 which are unaffected. Two SYSCLKS to first block clock. Figure 18-4. SPI Input Clocking PSoC CY8C20x34 TRM, Version 1.0 ...
Page 125
... TX Buffer register. Figure 18-6. Typical SPIM Timing in Mode 2 and 3 PSoC CY8C20x34 TRM, Version 1.0 ter. After the last bit is output Buffer data is available with one-half clock setup time to the next clock, a new byte transmission will be initiated. A SPIM block receives a byte at the same time that it sends one ...
Page 126
... RX Buffer register. Because the RX Buffer register is imple- mented as a latch, Overrun status is set one-half bit clock before RX Reg Full status. See Figure 18-7 and Figure 18-8 for status timing relation- ships. Transfer in Progress Transfer in Progress PSoC CY8C20x34 TRM, Version 1.0 ...
Page 127
... SCLK, Polarity=0 (Mode 2) SCLK, Polarity=1 (Mode 3) 7 MOSI 7 MISO SS_ TX REG EMPTY RX REG FULL SPI COMPLETE OVERRUN TX Buffer is transferred into the shifter Figure 18-8. SPI Status Timing for Modes 2 and 3 PSoC CY8C20x34 TRM, Version 1 Last bit of byte is received. ...
Page 128
... TX Buffer register). Last bit of received data is valid First input on this edge and is latched into bit is First the RX Buffer register. latched. Shift User writes the next byte to the TX Buffer register. and Figure 18-10. If the SPIS is pri PSoC CY8C20x34 TRM, Version 1.0 ...
Page 129
... Shift register is loaded from the TX Buffer register. All modes use the following mechanism there is no transfer in progress the shifter is empty, and 3) if data is PSoC CY8C20x34 TRM, Version 1.0 Last bit of received data is valid on this edge and is latched into First the RX Buffer register ...
Page 130
... SCLK in these modes. Transfer in Progress SCLK (Mode 2) SCLK (Mode 3) (No Dependance on SS) Figure 18-12. Mode 2 and 3 Transfer in Progress 130 Transfer in Progress Transfer in Progress PSoC CY8C20x34 TRM, Version 1.0 ...
Page 131
... Clock Registers CONFIGURATION[7:0] DATA[7:0] DATA[7:0] Figure 19-1. Programmable Timer Block Diagram PSoC CY8C20x34 TRM, Version 1.0 139. 19.1.1 Operation When started, the programmable timer loads the value con- tained in its data registers and counts down to its terminal count of zero. The timer outputs an active high terminal count pulse for one clock cycle upon reaching the terminal count ...
Page 132
... IRQ PTDATA1 0003h (13-bit) PTDATA0 Clock Start One Shot Count 00h 03h TC IRQ 132 02h 01h 00h 03h 02h 01h Figure 19-2. Continuous Operation Example 02h 01h 00h Figure 19-3. One Shot Operation Example 00h 03h 02h 01h 00h PSoC CY8C20x34 TRM, Version 1.0 ...
Page 133
... Bit 7 0,B2h PT_DATA0 The Programmable Timer Data Register 0 (PT_DATA0) holds the lower 8 bits of the progammable timer’s count value. PSoC CY8C20x34 TRM, Version 1.0 “Summary Table of the System Resource Registers” Bit 6 Bit 5 Bit 4 Bit 3 Bit 0: START. This bit starts the timer counting from a full count ...
Page 134
... Programmable Timer 134 PSoC CY8C20x34 TRM, Version 1.0 ...
Page 135
... Section E: The Registers section discusses the registers of the PSoC CY8C20x34 device. It lists all the registers in mapping tables, in address order. For easy reference, each register is linked to the page of a detailed description located in the next chapter. This section encompasses the following chapter: Register Reference on page 139 ...
Page 136
... INT_SW_EN E1 RW 176 155 INT_VC E2 RC 177 156 RES_WDT E3 W 178 157 E4 158 E5 159 E6 160 E7 161 162 F0 163 F1 164 CPU_F F7 RL 179 IDAC_D FD RW 180 CPU_SCR1 FE # 181 CPU_SCR0 FF # 182 PSoC CY8C20x34 TRM, Version 1.0 ...
Page 137
... RW 185 TMP_DR0 2D TMP_DR1 2E TMP_DR2 2F TMP_DR3 Gray fields are reserved. # Access is bit specific. PSoC CY8C20x34 TRM, Version 1 ...
Page 138
... Section E: Registers 138 PSoC CY8C20x34 TRM, Version 1.0 ...
Page 139
... 0,04h 1, 1,23h x, x,F7h Empty, grayed-out table cell PSoC CY8C20x34 TRM, Version 1.0 Description Multiple instances/address ranges of the same register Read register or bit(s) Write register or bit(s) Only a read/write register or bit(s). Logical register or bit(s) Clearable register or bit(s) Reset value is 0x00 or 00h Register is not reset ...
Page 140
... Data[7:0] Write value to port or read value from port. Reads return the state of the pin, not the value in the PRTxDR register. 140 PRT2DR : 0,08h Data[7:0] Register Definitions on page 57 in the GPIO chapter. 0,00h PRT3DR : 0,0Ch PSoC CY8C20x34 TRM, Version 1.0 ...
Page 141
... For additional information, refer to the Bit Name Description 7:0 Interrupt Enables[7:0] Bits enable the corresponding port pin interrupt PSoC CY8C20x34 TRM, Version 1.0 PRT2IE : 0,09h Interrupt Enables[7:0] Register Definitions on page 57 in the GPIO chapter. Port pin interrupt disabled for the corresponding pin. ...
Page 142
... Access : POR Bit Name This register is the SPI’s transmit data register. For additional information, refer to the Bit Name Description 7:0 Data[7:0] Data for selected function. 142 Data[7:0] Register Definitions on page 119 in the SPI chapter. 0,29h PSoC CY8C20x34 TRM, Version 1.0 ...
Page 143
... Access : POR Bit Name This register is the SPI’s receive data register. For additional information, refer to the Bit Name Description 7:0 Data[7:0] Data for selected function. PSoC CY8C20x34 TRM, Version 1 Data[7:0] Register Definitions on page 119 in the SPI chapter. SPI_RXR 0,2Ah ...
Page 144
... Data changes on the leading clock edge. Data is latched on the trailing edge (modes 2, 3). Non-inverted, clock idles low (modes 0, 2). Inverted, clock idles high (modes 1, 3). SPI function is not enabled. SPI function is enabled. 0,2Bh Clock Phase Clock Polarity Enable PSoC CY8C20x34 TRM, Version 1.0 ...
Page 145
... INTCAP[1:0] Select pins to enable connection of external integration capacitor in the charge integration mode. 00b 01b 10b 11b PSoC CY8C20x34 TRM, Version 1 ICAPEN[1:0] No capacitance Approximately 25 pF connected Approximately 50 pF connected Approximately 100 pF connected Neither P0[3] or P0[1] enabled P0[1] pin enabled ...
Page 146
... All bits in this register are reserved for PSoC devices with 256 bytes of SRAM. For additional information, refer to the Bit Name Description 7:0 Data[7:0] General purpose register space. 146 TMP_DR2 : x,6Eh Data[7:0] Register Definitions on page 36 in the RAM Paging chapter . x,6Ch TMP_DR3 : x,6Fh PSoC CY8C20x34 TRM, Version 1.0 ...
Page 147
... CMP0L Bit reads the latch output for comparator 0. This bit is cleared by either a write of ‘0’ to this bit rising edge of the comparator 1 LUT, depending on the state of the CRST0 bit in the CMP_CR1 reg- ister. PSoC CY8C20x34 TRM, Version 1 ...
Page 148
... Register Definitions on page 86 in the Comparators chapter . Analog Global Mux Bus Reserved P0[1] pin P0[3] pin VREF (1.3V) Ref Lo (approximately 0.9V) Ref Hi (approximately 1.8V) Reserved Analog Global Mux Bus Reserved P0[1] pin P0[3] pin VREF (1.3V) Ref Lo (approximately 0.9V) Ref Hi (approximately 1.8V) Reserved 0,79h INP0[1:0] INN0[1:0] PSoC CY8C20x34 TRM, Version 1.0 ...
Page 149
... CMP1EN CMP0R CMP0EN 0 1 PSoC CY8C20x34 TRM, Version 1 CMP1R CMP1EN Comparator 1 set to rail-to-rail input range, with approximately 20 µ A cell current. Comparator 1 set to limited input range (Vss to Vdd - 1V), with approximately 10 µ A cell cur- rent. Comparartor 1 disabled, powered off. ...
Page 150
... Comparartor 0 connects to the analog interrupt. A rising edge will assert that interrupt enabled in the INT_MSK0 register. Select Comparator 0 LUT output Select Comparator 0 Latch output Reset by writing a ‘0’ to the CMP_RDC register’s CMP0L bit Reset by rising edge of Comparator 1 LUT output 0,7Bh CPIN0 CRST0 CDS0 PSoC CY8C20x34 TRM, Version 1.0 ...
Page 151
... CMP_CR1 (continued) 0 CDS0 Bit selects the data output for the comparator 0 channel, for routing to the capacitive sense logic and comparator 0 interrupt PSoC CY8C20x34 TRM, Version 1.0 Select the Comparator 0 LUT output Select the Comparator 0 latch output CMP_CR1 0,7Bh 151 ...
Page 152
... NOR B A XNOR NAND B TRUE Function FALSE A AND B A AND AND XOR NOR B A XNOR NAND B TRUE 0,7Ch LUT0[3:0] PSoC CY8C20x34 TRM, Version 1.0 ...
Page 153
... CapSense Counter Mode 00b 01b 10b 11b PSoC CY8C20x34 TRM, Version 1 Selected Input CapSense Interrupt Carry Out Low Byte Carry Out High Byte Event mode. Start in Enable, stop on interrupt event. Pulse Width mode. Start on positive edge of next input. Stop on negative edge of input. ...
Page 154
... High byte counter runs on the RLO clock frequency. Selected input is not inverted. Selected input is inverted. Comparator 0 ILO Comparator 1 RLO Timer Terminal Count Interval Timer RLO Timer IRQ Analog Global Mux Bus ‘0’ 0,A1h INSEL[2:0] PSoC CY8C20x34 TRM, Version 1.0 ...
Page 155
... Bit provides manual connection of the IDAC to the analog global bus. The IDAC is automatically con- nected when RO_EN = 1 or PXD_EN = PXD_EN RO_EN 0 1 PSoC CY8C20x34 TRM, Version 1 IDACDIR IDAC_EN Register Definitions on page 76 in the CapSense Module chapter . IDAC output scaled to 1X range. IDAC output scaled to 2X range. ...
Page 156
... No connection of either comparator channel to low pass filter Connect comparator channel 0 through the low pass filter Connect comparator channel 1 through the low pass filter Connect both comparator channel inputs together, and through the low pass filter 0,A3h LPFilt[1:0] LPF_EN[1:0] PSoC CY8C20x34 TRM, Version 1.0 0 ...
Page 157
... Data[7: read of this register, the current count is returned. It may only be read when the counter is stopped. Note The counter must be stopped by the configured event. When the counter is disabled, the count is reset to 00h. PSoC CY8C20x34 TRM, Version 1 Data[7:0] Register Definitions on page 76 in the CapSense Module chapter ...
Page 158
... On a read of this register, the current count is returned. It may only be read when the counter is stopped. Note The counter must be stopped by the configured event. When the counter is disabled, the count is reset to 00h. 158 Data[7:0] Register Definitions on page 76 in the CapSense Module chapter . 0,A5h PSoC CY8C20x34 TRM, Version 1.0 ...
Page 159
... Counter Carry Out Low Interrupt Mask COHM Counter Carry Out High Interrupt Mask PPM Pulse Width/Period Measurement Interrupt Mask 0 1 PSoC CY8C20x34 TRM, Version 1 COHS PPS INM Register Definitions on page 76 in the CapSense Module chapter . No event detected A rising edge on the selected input was detected. Cleared by writing a ‘ ...
Page 160
... Reserved bits should always be written with a value of ‘0’. For additional information, refer to the 76 in the CapSense Module chapter . Bit Name Description 5:0 Timer Count Value[5:0] Holds the timer count value. 160 Timer Count Value[5:0] 0,A7h Register Definitions on page PSoC CY8C20x34 TRM, Version 1.0 ...
Page 161
... IRANGE bits. 0000000b 0000001b … 1111111b 0 FS_EN Enable bit for the Fast Slew mode 0 1 PSoC CY8C20x34 TRM, Version 1 FastSlew[6:0] Register Definitions on page 76 in the CapSense Module chapter . No fast edge rate interval Minimum fast edge rate interval (1 IMO period) Maximum fast edge rate interval (127 IMO period) Fast slew mode disabled ...
Page 162
... Timer counts down from a full count determined from its data registers (PT_DATA1, PT_DATA0). When complete, it will either stop or reload and continue, based on the One Shot bit in this register. 0,B0h One Shot START Register Definitions on page PSoC CY8C20x34 TRM, Version 1.0 ...
Page 163
... In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the 133 in the Programmable Timer chapter . Bit Name Description 4:0 Data[4:0] Holds upper 5 bits of 13-bit count value. PSoC CY8C20x34 TRM, Version 1 DATA[4:0] PT_DATA1 0,B1h 0,B1h 2 1 ...
Page 164
... This register is used to provide the programmable timer with its lower 8 bits of the count value. For additional information, refer to the Bit Name Description 7:0 Data[7:0] Holds lower 8 bits of 13-bit count value. 164 Data[7:0] Register Definitions on page 133 in the Programmable Timer chapter . 0,B2h PSoC CY8C20x34 TRM, Version 1.0 ...
Page 165
... Page Bit Bit determines which SRAM page is used for generic SRAM access. See the page Note A value beyond the available SRAM, for a specific PSoC device, should not be set. PSoC CY8C20x34 TRM, Version 1 for more information. SRAM Page 0 SRAM Page 1 ...
Page 166
... Page Bit for more information Note A value beyond the available SRAM, for a specific PSoC device, should not be set. 166 SRAM Page 0 SRAM Page 1 0,D1h Page Bit Register Definitions on page RAM Paging chapter on page 33 PSoC CY8C20x34 TRM, Version 1.0 ...
Page 167
... Bit determines which SRAM page an indexed memory access operates on. See the tions on page Note A value beyond the available SRAM, for a specific PSoC device, should not be set. PSoC CY8C20x34 TRM, Version 1 for more information on when this register is active. SRAM Page 0 ...
Page 168
... Bit determines which SRAM page a MVI Read instruction operates on. 0 Page Bit 0b 1b Note A value beyond the available SRAM, for a specific PSoC device, should not be set. 168 SRAM Page 0 SRAM Page 1 0,D4h Page Bit Register Definitions on page PSoC CY8C20x34 TRM, Version 1.0 ...
Page 169
... RAM Paging chapter . Bit Name Description 0 Page Bit Bit determines which SRAM page a MVI Write instruction operates on Note A value beyond the available SRAM, for a specific PSoC device, should not be set. PSoC CY8C20x34 TRM, Version 1 SRAM Page 0 SRAM Page 1 MVW_PP 0,D5h 0,D5h 2 ...
Page 170
... Stop IE Clock Rate[1:0] P1[5] and P1[7] P1[0] and P1[1] Disabled Enabled. An interrupt is generated on the detection of a Stop condition. 100K Standard Mode 400K Fast Mode 50K Standard Mode Reserved Disabled Enabled 0,D6h Enable Register Definitions on page PSoC CY8C20x34 TRM, Version 1.0 ...
Page 171
... Byte Complete Transmit/Receive Mode: 0 Transmit Mode: 1 Receive Mode: 1 PSoC CY8C20x34 TRM, Version 1 Stop Status ACK Address Status bit. It must be cleared by firmware by writing a ‘0’ to the bit position never cleared by the hardware. ...
Page 172
... This register is read only for received data and write only for transmitted data. For additional information, refer to the Bit Name Description 7:0 Data[7:0] Read received data or write data to transmit 172 Data[7:0] Register Definitions on page 100 in the I2C Slave chapter . 0,D8h PSoC CY8C20x34 TRM, Version 1.0 ...
Page 173
... Read 1 Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect Write 0 AND ENSWINT = 1 No effect Write 1 AND ENSWINT = 1 Post an interrupt for general purpose inputs and outputs (pins). (continued on next page) PSoC CY8C20x34 TRM, Version 1 ...
Page 174
... No posted interrupt for Timer. Posted interrupt present for Timer. No posted interrupt for CapSense. Posted interrupt present for CapSense. No posted interrupt for analog. Posted interrupt present for analog. No posted interrupt for supply voltage monitor. Posted interrupt present for supply voltage monitor. PSoC CY8C20x34 TRM, Version 1.0 ...
Page 175
... Timer CapSense Analog Monitor 0 1 PSoC CY8C20x34 TRM, Version 1 SPI GPIO Timer Register Definitions on page 49 in the Interrupt Controller chapter. Mask I2C interrupt Unmask I2C interrupt Mask sleep interrupt Unmask sleep interrupt Mask SPI interrupt ...
Page 176
... Reserved bits should always be written with a value of ‘0’. For additional information, refer to the 49 in the Interrupt Controller chapter. Bit Name 0 ENSWINT 0 1 176 Description Disable software interrupts Enable software interrupts 0,E1h ENSWINT Register Definitions on page PSoC CY8C20x34 TRM, Version 1.0 ...
Page 177
... Bit Name This register returns the next pending interrupt and clears all pending interrupts when written. For additional information, refer to the Bit Name 7:0 Pending Interrupt[7:0] PSoC CY8C20x34 TRM, Version 1 Pending Interrupt[7:0] Register Definitions on page 49 in the Interrupt Controller chapter. ...
Page 178
... For additional information, refer to the Bit Name Description 7:0 WDSL_Clear[7:0] Any write clears the watchdog timer. A write of 38h clears both the watchdog and sleep timers. 178 WDSL_Clear[7:0] Register Definitions on page 65 in the Sleep and Watchdog chapter. 0,E3h PSoC CY8C20x34 TRM, Version 1.0 ...
Page 179
... Set by the M8C CPU Core to indicate whether there has been a zero result in the previous logical/ arithmetic operation GIE 0 1 PSoC CY8C20x34 TRM, Version 1 XIO Direct Address mode and Indexed Address mode operands are referred to RAM Page 0, regardless of the values of CUR_PP and IDX_PP. Note that this condition prevails on entry to an Interrupt Service Routine when the CPU_F register is cleared ...
Page 180
... Step size is approximately 330 nA/bit for default IRANGE state 00b. 00h . . . FFh 180 IDACDATA[7:0] Register Definitions on page 76 in the CapSense Module chapter. Smallest current (nominally zero unless IBOOST bit is set in the CS_CR3 register). Largest current 0,FDh PSoC CY8C20x34 TRM, Version 1.0 ...
Page 181
... Reduces frequency of the internal main oscillator (IMO). This bit is reserved on PSoC devices that do not support the slow IMO (see the IRAMDIS 0 1 PSoC CY8C20x34 TRM, Version 1 SLIMO Boot phase only executed once. Boot phase occurred multiple times. Architectural Description on page ...
Page 182
... Power On Reset has not occurred and watchdog timer is enabled. Will be set after external reset or Power On Reset. Normal operation Sleep M8C is free to execute code. M8C is halted. Can only be cleared by POR, XRES, or WDR. x,FFh STOP Register Definitions on page 110 in the PSoC CY8C20x34 TRM, Version 1.0 ...
Page 183
... Bit 0 of the Drive mode, for each of 8-port pins, for a GPIO port Note A bold digit, in the table above, signifies that the digit is used in this register. PSoC CY8C20x34 TRM, Version 1.0 Bank 0 Registers on page 140. PRT2DM0 : 1,08h ...
Page 184
... PRTxDM0 on page 183). The bit position of Pin Output Low Notes Strong Strong High-Z Reset state. Digital input disabled for zero power. Strong I2C compatible mode. For digital inputs, use this mode with data bit (PRTxDR register) set high. PSoC CY8C20x34 TRM, Version 1.0 ...
Page 185
... SS_ Slave Select in Slave mode SS_EN_ Internal Slave Select Enable 0 1 Interrupt Select 1 Int Sel Slave 1 PSoC CY8C20x34 TRM, Version 1 Bypass SS_ Register Definitions on page 119 in the SPI chapter 128 / 256 All pin unputs are doubled, synchronized Input synchronization is bypassed ...
Page 186
... MUX_CR2 : 1,DAh ENABLE[7:0] Register Definitions on page 84 in the IO Analog Multiplexer chapter. No connection between port pin and analog mux bus. Connect port pin to analog mux bus. 1,D8h MUX_CR3 : 1,DBh PSoC CY8C20x34 TRM, Version 1.0 ...
Page 187
... Sets the GPIO interrupt mode for all pins in the PSoC device. GPIO interrupts are also controlled at each pin by the PRTxIE registers, and by the global GPIO bit in the INT_MSK0 register PSoC CY8C20x34 TRM, Version 1 Regulator disabled, so Port 1 strong outputs drive to Vdd. ...
Page 188
... Select CapSense output signal (CS). This signal is selected by the CSOUT[1:0] bits in the CS_CR0 register. No internal signal output to P1[2] Output the signal selected by P12D to P1[2] Select Sleep Interrupt (SLPINT) Select Comparator 0 Output (CMP0) No internal signal output to P1[0] Output the signal selected by P10D to P1[0] 1,DDh P12EN P10D P10EN PSoC CY8C20x34 TRM, Version 1.0 ...
Page 189
... MHz or be driven from an external clock. 000b 001b 010b 011b 100b 101b 110b 111b PSoC CY8C20x34 TRM, Version 1 Buzz Sleep[1:0] No effect on buzz modes Buzz is disabled during sleep, with bandgap powered down. No periodic wakeup of the bandgap during sleep ...
Page 190
... Also, this bit must not be set high if the external clock fre- quency is less than 6 MHz. When switching from external clock to internal clock, the IMO must be enabled for at least 10 µ s before the transition to internal clock. Refer to 1,E2h EXTCLKEN IMODIS Register Definitions on page Switch Operation on page 92. PSoC CY8C20x34 TRM, Version 1.0 ...
Page 191
... PSoC devices with this feature. 000b 001b 010b 011b 100b 101b 110b 111b PSoC CY8C20x34 TRM, Version 1 PORLEV[1:0] LVDTBEN POR level for 2.4 V operation (refer to the PSoC device data sheet) POR level for 2.7V operation (refer to the PSoC device data sheet) POR level for 3 ...
Page 192
... Sufficient voltage for Flash write. Insufficient voltage for Flash write. Vdd is above LVD trip point. Vdd is below LVD trip point. Vdd is above PPOR trip voltage. Vdd is below PPOR trip voltage. 1,E4h LVD PPOR Register Definitions on page 115 in the PSoC CY8C20x34 TRM, Version 1.0 ...
Page 193
... The value of these bits should not be changed unless Slow IMO mode is used . 00h 01h ... 7Fh 80h 81h ... FEh FFh PSoC CY8C20x34 TRM, Version 1 Trim[7:0] Register Definitions on page 60 in the Internal Main Oscillator chapter. Lowest frequency setting ... Design center setting ...
Page 194
... The value of this register is used to trim the Internal Low Speed Oscillator. Its value is set to the device specific, best value during boot. The value of these bits should not be changed. 194 Bias Trim[1:0] Medium bias Maximum bias (recommended) Minimum bias Intermediate Bias * 1,E9h Freq Trim[3:0] Register Definitions on page PSoC CY8C20x34 TRM, Version 1.0 ...
Page 195
... V[4:0] The value of these bits is used to trim the bandgap reference. Their value is set to the best value for the device during boot. The value of these bits should not be changed. PSoC CY8C20x34 TRM, Version 1 Register Definitions on page 108 in the Internal Voltage References chapter. ...
Page 196
... Sleep Duty Cycle. Controls the ratios (in numbers of 32.768 kHz clock periods) of “on” time versus “off” time for PORLVD4, bandgap reference. The value of these bits should not be changed. 00b 01b 10b 11b 196 256 (8 ms 1024 (31 (500 ms) 1,EBh Register Definitions on page PSoC CY8C20x34 TRM, Version 1.0 ...
Page 197
... A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. AND See Boolean Algebra . PSoC CY8C20x34 TRM, Version 1.0 Glossary 197 ...
Page 198
... A single digit of a binary number. Therefore, a bit may only have a value of ‘0’ or ‘1’. A group of 8 bits is called a byte. Because the PSoC's M8C is an 8-bit microcontroller, the PSoC's native data chunk size is a byte. 198 , to produce a zero temperature coefficient (ideally) BE PSoC CY8C20x34 TRM, Version 1.0 with T ...
Page 199
... A measure of the ability of two adjacent conductors, separated by an insulator, to hold a charge when a voltage differential is applied between them. Capacitance is measured in units of Farads. capture To extract information automatically through the use of software or hardware, as opposed to hand-entering of data into a computer file. PSoC CY8C20x34 TRM, Version 1.0 Section F: Glossary 199 ...
Page 200
... More generally, a set of signals used to convey data between digital functions. data stream A sequence of digitally encoded signals used to represent information in transmission. data transmission The sending of data from one place to another by means of signals over a channel. 200 PSoC CY8C20x34 TRM, Version 1.0 ...