CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 65

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

9.3
The following registers are associated with Sleep and Watchdog and are listed in address order. Each register description has
an associated register table showing the bit structure for that register. The bits that are grayed out in the tables below are
reserved bits and are not detailed in the register descriptions. Reserved bits should always be written with a value of ‘0’. For a
complete table of the Sleep and Watchdog registers, refer to the
9.3.1
The Reset Watchdog Timer Register (RES_WDT) is used to
clear the watchdog timer (a write of any value) and clear
both the watchdog timer and the sleep timer (a write of 38h).
Bits 7 to 0: WDSL_Clear[7:0]. The
(WDT) write-only register is designed to timeout at three roll-
over events of the sleep timer. Therefore, if only the WDT is
cleared, the next Watchdog Reset (WDR) will occur any-
where from two to three times the current sleep interval set-
ting. If the sleep timer is near the beginning of its count, the
watchdog timeout will be closer to three times. However, if
9.3.2
The Sleep Configuration Register (SLP_CFG) is used to set
the sleep duty cycle.
The value placed in this register is based on factory testing.
It is strongly recommended that the user not alter the
register value.
9.3.3
PSoC CY8C20x34 TRM, Version 1.0
0,E3h
1,EBh
Address
Address
“INT_MSK0 Register” on page
“OSC_CR0 Register” on page
“ILO_TR Register” on page
“CPU_SCR0 Register” on page
“CPU_SCR1 Register” on page
Register Definitions
RES_WDT
SLP_CFG
RES_WDT Register
SLP_CFG Register
Related Registers
Name
Name
Bit 7
Bit 7
PSSDC[1:0]
61.
95.
50.
111.
110.
Bit 6
Bit 6
Watchdog
Bit 5
Bit 5
Timer
Bit 4
Bit 4
WDSL_Clear[7:0]
the sleep timer is very close to its terminal count, the
watchdog timeout will be closer to two times. To ensure a full
three times timeout, both the WDT and the sleep timer may
be cleared. In applications that need a real-time clock, and
thus cannot reset the sleep timer when clearing the WDT,
the duty cycle at which the WDT must be cleared should be
no greater than two times the sleep interval.
For additional information, refer to the
on page
Bits 7 and 6: PSSDC[1:0]. The Power System Sleep Duty
Cycle bits are used to set the sleep duty cycle. These bits
should not be altered.
For additional information, refer to the
page
“Summary Table of the Core Registers” on page
196.
Bit 3
Bit 3
178.
Bit 2
Bit 2
Bit 1
Bit 1
SLP_CFG register on
Sleep and Watchdog
RES_WDT register
Bit 0
Bit 0
24.
RW : 00
Access
Access
W : 00
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